On Fri, Sep 4, 2020 at 7:47 AM Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
>
> From: "sebastian.huber" <sebastian.huber@ad346e48-6743-2946-b04c-964484d2d4e6>
>
git-config problem
> In a multi-processor system we must broadcast the TLB maintenance operation to
> the Inner Shareable domain to ensure that the other processors update their
> TLB
> caches accordingly.
>
> Close #4068.
> ---
> bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 2 +-
> cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
> b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
> index 507277dca1..976f87a36e 100644
> --- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
> +++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
> @@ -107,7 +107,7 @@ static uint32_t set_translation_table_entries(
> #define MPIDR_UP (1 << 30)
> const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity();
> if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) {
> - arm_cp15_tlb_invalidate_entry_all_asids(mva);
> + arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(mva);
> }
> else
> #endif
> diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
> b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
> index 8d43ca0ac2..6097d60ba6 100644
> --- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
> +++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
> @@ -646,6 +646,22 @@ arm_cp15_tlb_invalidate_entry_all_asids(const void *mva)
> );
> }
>
> +ARM_CP15_TEXT_SECTION static inline void
> +arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(const void *mva)
> +{
> + ARM_SWITCH_REGISTERS;
> +
> + mva = ARM_CP15_TLB_PREPARE_MVA(mva);
> +
> + __asm__ volatile (
> + ARM_SWITCH_TO_ARM
> + "mcr p15, 0, %[mva], c8, c3, 3\n"
> + ARM_SWITCH_BACK
> + : ARM_SWITCH_OUTPUT
> + : [mva] "r" (mva)
> + );
> +}
> +
> ARM_CP15_TEXT_SECTION static inline void
> arm_cp15_tlb_instruction_invalidate(void)
> {
> --
> 2.26.2
>
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