We've patched the RTEMS kernel in order to support using the Zynq on-chip
memory as inner-cacheable memory. The enclosed patch should apply cleanly
to master.
Background: During normal startup, the ROM bootloader performs
vendor-specific initialization of core 1, and then sits in a
wait-for-event loop until a special value has been written to a specific
address in OCM. In that state, the MMU has not yet been initialized and
core 1 is treating OCM as Device memory.
By the time the RTEMS boot gets to _CPU_SMP_Start_processor, core 0's MMU
has already been initialized with the application-defined memory map. I'd
like to use the on-chip memory as inner cacheable memory in my
application. In order to ensure that the kick address write actually
becomes visible to core 1, a cache line flush of the affected line is
necessary prior to sending the event that wakes up the other core.
I also added an invalidation prior to the kick-address write out of an
abundance of caution. it shouldn't be necessary, but I had a hard time
proving it definitively.
There are a plethora of cache maintenance functions available for the job
in RTEMS. I picked an inline helper that operates directly on CP15. The
code's commentary suggests that the L2 hasn't been initialized yet, and the
higher-level `rtems_cache_*_multiple_data_lines` API affects both L1D and
L2. Also, I'm using inner-cacheable/outer-shareable memory attributes for
OCM specifically because of where it sits in the SOC's busswork, so it
turns out that we *never* need to flush L2 for that memory anyway.
--
Jonathan Brandmeyer
PlanetiQ
From 56b57b8e6933316827ebd75990bdc96b189c2adf Mon Sep 17 00:00:00 2001
From: Jonathan Brandmeyer <jbrandmeyer@planetiq.com>
Date: Wed, 10 Jun 2020 17:09:57 -0600
Subject: [PATCH] bsp: Support cacheable OCM on the Zynq
... by issuing L1D-specific cache invalidation and flushing instructions
around the kick address.
---
bsps/arm/xilinx-zynq/start/bspsmp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/bsps/arm/xilinx-zynq/start/bspsmp.c b/bsps/arm/xilinx-zynq/start/bspsmp.c
index fdb7f85ba6..d6e8759b95 100644
--- a/bsps/arm/xilinx-zynq/start/bspsmp.c
+++ b/bsps/arm/xilinx-zynq/start/bspsmp.c
@@ -28,6 +28,7 @@
#include <rtems/score/smpimpl.h>
#include <bsp/start.h>
+#include <libcpu/arm-cp15.h>
bool _CPU_SMP_Start_processor(uint32_t cpu_index)
{
@@ -36,11 +37,14 @@ bool _CPU_SMP_Start_processor(uint32_t cpu_index)
*/
if (cpu_index != 0) {
volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
+ arm_cp15_data_cache_invalidate_line((void *)kick_address);
_ARM_Data_synchronization_barrier();
_ARM_Instruction_synchronization_barrier();
*kick_address = (uint32_t) _start;
_ARM_Data_synchronization_barrier();
_ARM_Instruction_synchronization_barrier();
+ arm_cp15_data_cache_clean_and_invalidate_line((const void *)kick_address);
+ _ARM_Data_synchronization_barrier();
_ARM_Send_event();
}
--
2.20.1
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