> On Jan 31, 2020, at 15:22 , Peter Dufault <dufa...@hda.com> wrote:
>
> I noticed this while tracking down the GMAC transmit initialization on
> non-revA SAMV71 chips and wanted to send it as heads-up and to see if anyone
> understands what's happening.
>
> If I left the board doing nothing then after about fifteen or twenty minutes
> (I never characterized it) I would see "External reset detected" in the
> "ocd-remote" window and the program would restart. I put breakpoints in the
> RTEMS fatal exit and it was never called, so I suspected a watch-dog timer
> reset. I checked the RTEMS code and couldn't see anywhere the watch-dog was
> programmed. I checked on-line:
>
> "The Watchdog Timer (WDT) is used to prevent system lock-up if the software
> becomes trapped in a deadlock. It features a 12-bit down counter that allows
> a watchdog period of up to 16 seconds (slow the clock to around 32kHz). It
> can generate a general reset or a processor reset only. In addition, it can
> be stopped while the processor is in debug mode or idle mode.
>
> "After a processor reset, the Watchdog peripheral is enabled by default with
> the value of watchdog counter value equal to 0xFFF, which corresponds to the
> maximum value of the counter with the external reset generation enabled (bit
> WDT_MR.WDRSTEN at 1 after a backup reset). The user can either disable the
> WDT by setting bit WDT_MR.WDDIS or reprogram the WDT to meet the maximum
> watchdog period the application requires."
>
> This implies the board will get an external reset after sixteen seconds, not
> fifteen or twenty minutes, if the behavior isn't changed, but I added a
> "WDT_Disable(WDT);" to my code anyway and that solved the problem.
>
> I posted this to give anyone else a heads-up and also to find out if anyone
> understood why it would take so long for the WDT to kick in.
>
>
>
Never mind. I re-read my post as it came in in the email and I immediately
knew what the problem was: the default watchdog triggers at 18.20444444444(...)
minutes.
The watchdog *period* is initialized to about 16 seconds, and the watchdog
*countdown* is initialized to 4096. The result is the default watchdog *reset*
happens after about 18 minutes.
Oh well, reviewing what you've sent to the world frequently provides insight.
Anyway, BSP users still need to know they need to either tickle the watchdog or
put it to sleep when they use this BSP.
Peter
-----------------
Peter Dufault
HD Associates, Inc. Software and System Engineering
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