On 25/10/19 8:41 am, Chris Johns wrote: > On 24/10/19 7:50 pm, Sebastian Huber wrote: >> On 24/10/2019 03:41, Jonathan Brandmeyer wrote: >>> On Wed, Oct 23, 2019 at 6:04 AM Thomas Doerfler >>> <thomas.doerf...@embedded-brains.de> wrote: >>>> >>>> Hi, >>>> >>>> most likely the RAM areas have been mapped to the lowest-possible >>>> non-NULL address, and they can be mapped to an address boundary matching >>>> the RAM size. zc702 has a 1MByte ram, mapped to the 1MByte boundary, >>>> zc706 has a 4MByte RAM mapped to the 4MByte boundary. >>> >>> I don't know what the actual rationale is, but this definitely isn't >>> it. The DDR physical address mapping is fixed. The lower 256k can be >>> mapped to DRAM or on-chip SRAM depending on system settings. The >>> range from 256k - 1M is either inaccessible or mapped to DRAM. The >>> range from 1M - 4M is always mapped to DRAM. Its an >>> application-profile processor, which is why the typical sizes are 512M >>> or 1024M (SoC maximum) for DRAM. >>> >>> See also Xilinx UG585, section 4.1. >>> >>> The chip's reset defaults are for 192 kB of OCM to be mapped low, and >>> 64 kB to be mapped high with address filtering disabled. >> >> >> Yes, the DDR is surly greater than 4MiB. The unused 1MiB starting a 0 is >> there >> to catch NULL pointer access (read, write, and execute). Why the >> xilinx_zynq_zc706 has an unused 4MiB area is not clear to me. > > It is not clear to me either. I am fine with the start address being the same > for all variants. If nothing else someone may speak up and we will find out > the > reason.
I have looked into this and there are systems where memory is reserved below the executable away from RTEMS. This is a valid address for those cases. I am fine if the base address can be configured. Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
