On 26/07/2019 07:37, Chris Johns wrote:
On 26/7/19 3:06 pm, Sebastian Huber wrote:
Hello Chris,
I am not sure, if using r8 is the right thing to do since r8..r14 are banked in
FIQ mode.
The ARM docs I referenced say the register is general purpose. There is other
docs they say something else?
This is a standard ARM feature, see for example "B1.3.2
ARM core registers" in the ARMv7-AR reference manual.
This is early boot code who why would FIQ banks be an issue? Which BSPs would
that effect?
You set the stack in FIQ mode in start.S:
/* Initialize stack pointer registers for the various modes */
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
mov sp, r8
sub r8, r8, r1
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_banked_fiq
#endif
I think the bsp_start_arm_drop_hyp_mode needs to be changed to not
touch r3, it can use r1 instead.
That is a bad idea. The registers are documented as scratch and it's use here
across a call is wrong.
We are here in the low level startup code, so we have to be a bit
flexible if it comes to the ABI. We should move these low level
functions to start.S.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
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