Hi,
Thank you for these changes. It is nice to see doxygen support being improved.
Could I please suggest the first line of the commit message has `doxygen` in it,
such as 'doxygen: score: Add Blackfin CPU architecture group' so a compact git
log report of just the first line indicates the patch is only doxygen? The
message for this patch could mean a few things and for someone new to the code
base it could mean anything.
Thanks
Chris
On 29/3/19 9:52 pm, Sebastian Huber wrote:
> From: Andreas Dachsberger <andreas.dachsber...@embedded-brains.de>
>
> Update #3706.
> ---
> cpukit/score/cpu/bfin/include/rtems/score/cpu.h | 36
> ++++++++++++----------
> .../score/cpu/bfin/include/rtems/score/cpuimpl.h | 12 ++++++++
> 2 files changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
> b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
> index 481762d7b8..4b4e5b5868 100644
> --- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
> @@ -191,7 +191,7 @@ extern "C" {
> #define CPU_STRUCTURE_ALIGNMENT
>
> /**
> - * @ingroup CPUInterrupt
> + * @addtogroup RTEMSScoreCPUBfinCPUInterrupt
> * The following defines the number of bits actually used in the
> * interrupt field of the task mode. How those bits map to the
> * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
> @@ -217,7 +217,9 @@ extern "C" {
> #ifndef ASM
>
> /**
> - * @defgroup CPUContext Processor Dependent Context Management
> + * @defgroup RTEMSScoreCPUBfinCPUContext Processor Dependent Context
> Management
> + *
> + * @ingroup RTEMSScoreCPUBfin
> *
> * From the highest level viewpoint, there are 2 types of context to save.
> *
> @@ -312,9 +314,12 @@ typedef struct {
> /** @} */
>
> /**
> - * @defgroup CPUInterrupt Processor Dependent Interrupt Management
> + * @defgroup RTEMSScoreCPUBfinCPUInterrupt Processor Dependent Interrupt
> Management
> + *
> + * @ingroup RTEMSScoreCPUBfin
> */
> -/**@{**/
> +/** @{ **/
> +/** @} **/
>
> /*
> * Nothing prevents the porter from declaring more CPU specific variables.
> @@ -327,7 +332,7 @@ typedef struct {
> /* XXX: if needed, put more variables here */
>
> /**
> - * @ingroup CPUContext
> + * @addtogroup RTEMSScoreCPUBfinCPUContext
> * The size of the floating point context area. On some CPUs this
> * will not be a "sizeof" because the format of the floating point
> * area is not defined -- only the size is. This is usually on
> @@ -342,6 +347,7 @@ typedef struct {
> #endif /* ASM */
>
> /**
> + * @addtogroup RTEMSScoreCPUBfinCPUInterrupt
> * Amount of extra stack (above minimum stack size) required by
> * MPCI receive server thread. Remember that in a multiprocessor
> * system this thread must exist and be able to process all directives.
> @@ -353,7 +359,7 @@ typedef struct {
> #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
>
> /**
> - * @ingroup CPUInterrupt
> + * @addtogroup RTEMSScoreCPUBfinCPUInterrupt
> * This defines the number of entries in the @ref _ISR_Vector_table managed
> * by RTEMS.
> *
> @@ -364,22 +370,20 @@ typedef struct {
> #define CPU_INTERRUPT_NUMBER_OF_VECTORS 16
>
> /**
> - * @ingroup CPUInterrupt
> + * @addtogroup RTEMSScoreCPUBfinCPUInterrupt
> * This defines the highest interrupt vector number for this port.
> */
> #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
> (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
>
> /**
> - * @ingroup CPUInterrupt
> + * @addtogroup RTEMSScoreCPUBfinCPUInterrupt
> * This is defined if the port has a special way to report the ISR nesting
> * level. Most ports maintain the variable @a _ISR_Nest_level.
> */
> #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
>
> -/** @} */
> -
> /**
> - * @ingroup CPUContext
> + * @addtogroup RTEMSScoreCPUBfinCPUContext
> * Should be large enough to run all RTEMS tests. This ensures
> * that a "reasonable" small application should not have any problems.
> *
> @@ -450,7 +454,7 @@ typedef struct {
> */
>
> /**
> - * @addtogroup CPUInterrupt
> + * @addtogroup RTEMSScoreCPUBfinCPUInterrupt
> */
> /**@{**/
>
> @@ -555,7 +559,7 @@ uint32_t _CPU_ISR_Get_level( void );
> /* Context handler macros */
>
> /**
> - * @ingroup CPUContext
> + * @addtogroup RTEMSScoreCPUBfinCPUContext
> * Initialize the context to a state suitable for starting a
> * task after a context restore operation. Generally, this
> * involves:
> @@ -675,7 +679,7 @@ void _CPU_ISR_install_vector(
> void *_CPU_Thread_Idle_body( uintptr_t ignored );
>
> /**
> - * @addtogroup CPUContext
> + * @addtogroup RTEMSScoreCPUBfinCPUContext
> */
> /**@{**/
>
> @@ -752,7 +756,7 @@ typedef CPU_Interrupt_frame CPU_Exception_frame;
> void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
>
> /**
> - * @ingroup CPUEndian
> + * @addtogroup CPUEndian
> * The following routine swaps the endian format of an unsigned int.
> * It must be static because it is referenced indirectly.
> *
> @@ -795,7 +799,7 @@ static inline uint32_t CPU_swap_u32(
> }
>
> /**
> - * @ingroup CPUEndian
> + * @addtogroup CPUEndian
> * This routine swaps a 16 bir quantity.
> *
> * @param[in] value is the value to be swapped
> diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
> b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
> index 78b87ef981..2140487fc3 100644
> --- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
> +++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
> @@ -17,6 +17,16 @@
>
> #include <rtems/score/cpu.h>
>
> +/**
> + * @defgroup RTEMSScoreCPUBfin Blackfin
> + *
> + * @ingroup RTEMSScoreCPU
> + *
> + * @brief Blackfin Architecture Support
> + *
> + * @{
> + */
> +
> #define CPU_PER_CPU_CONTROL_SIZE 0
>
> #ifndef ASM
> @@ -53,4 +63,6 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation(
> void )
>
> #endif /* ASM */
>
> +/** @} */
> +
> #endif /* _RTEMS_SCORE_CPUIMPL_H */
>
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