On 21/01/2019 16:49, Jiri Gaisler wrote:
Fourth take on adding a bsp for a RISC-V GRLIB cpu, taking into account
previous comments.
Jiri Gaisler (6):
grlib: Fix inludes
grlib: make apbuart driver independent of bsp
grlib: use rtems_interrupt_handler_install() for all interrupt
handlers
grlib: use cpu-independent routines for uncached access
grlib: make memory coherency cpu-independent
riscv: add griscv bsp
Sebastian Huber (2):
grlib: Move header files
grlib: Move source files
I added a ticket for this BSP:
http://devel.rtems.org/ticket/3678
I checked in a slightly modified patch set. For example to fix build
errors with the leon2 BSP. I added also a documentation stub:
https://docs.rtems.org/branches/master/user/bsps/bsps-riscv.html#griscv
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
