This looks like a good approach. If 0 is a valid instruction on
some architecture, we can add a conditional.
On Thu, Jul 19, 2018 at 5:55 AM, Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On some architectures/simulators it is difficult to provoke an
> exception with misaligned or illegal data loads. Use an illegal
> instruction instead.
>
> Update #3433.
> ---
> testsuites/sptests/spfatal26/init.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/testsuites/sptests/spfatal26/init.c b/testsuites/sptests/
> spfatal26/init.c
> index 1848659d6a..7d635f3b84 100644
> --- a/testsuites/sptests/spfatal26/init.c
> +++ b/testsuites/sptests/spfatal26/init.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2012 embedded brains GmbH. All rights reserved.
> + * Copyright (c) 2012, 2018 embedded brains GmbH. All rights reserved.
> *
> * embedded brains GmbH
> * Obere Lagerstr. 30
> @@ -24,6 +24,13 @@
>
> const char rtems_test_name[] = "SPFATAL 26";
>
> +static void provoke_illegal_instruction_exception( void )
> +{
> +#ifdef __riscv
> + __asm__ volatile (".word 0");
> +#endif
> +}
> +
> static void provoke_aligment_or_data_access_exception( void )
> {
> uintptr_t one = 1;
> @@ -53,6 +60,7 @@ static void Init( rtems_task_argument arg )
> {
> TEST_BEGIN();
>
> + provoke_illegal_instruction_exception();
> provoke_aligment_or_data_access_exception();
>
> rtems_test_assert( 0 );
> --
> 2.13.7
>
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>
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