On Thu, Jul 12, 2018 at 9:44 PM, Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > ----- Am 6. Jul 2018 um 16:35 schrieb Hesham Almatary > heshamelmat...@gmail.com: > >> On Fri, Jun 29, 2018 at 10:57 AM, Sebastian Huber <s...@rtems.org> wrote: >>> Module: rtems >>> Branch: master >>> Commit: c558cc4b00f00b6746eec3a249a7a79995cea7cf >>> Changeset: >>> http://git.rtems.org/rtems/commit/?id=c558cc4b00f00b6746eec3a249a7a79995cea7cf >>> >>> Author: Sebastian Huber <sebastian.hu...@embedded-brains.de> >>> Date: Thu Jun 28 13:04:58 2018 +0200 >>> >>> bsp/riscv: Fix vector table for lp64 >>> >>> Update #3433. >>> >>> --- >>> >>> bsps/riscv/riscv/start/start.S | 38 ++++++++++++++++++++++---------------- >>> 1 file changed, 22 insertions(+), 16 deletions(-) >>> >>> diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S >>> index b59e55f..390459a 100644 >>> --- a/bsps/riscv/riscv/start/start.S >>> +++ b/bsps/riscv/riscv/start/start.S >>> @@ -104,22 +104,28 @@ SYM(_start): >>> .word 0xdeadbeef >>> #endif >>> >>> +#if __riscv_xlen == 32 >>> +#define ADDR .word >>> +#elif __riscv_xlen == 64 >>> +#define ADDR .quad >> Out of curirosity, why is it .quad and not .dword? > > I cannot find a .dword in the GNU as documentation. Right. I didn't know this. It's just in the RISC-V assembly book [1]. Just got confused thinking .quad is 128-bit as I haven't used it before.
[1] https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md -- Hesham _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
