Add CPU port define for the interrupt stack alignment. The alignment
should take the stack ABI and the cache line size into account.
Update #3459.
---
cpukit/score/cpu/arm/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/bfin/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/epiphany/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/i386/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/lm32/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/m32c/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/m68k/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/mips/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/moxie/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/nios2/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h | 8 ++++++++
cpukit/score/cpu/or1k/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/powerpc/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/sh/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/sparc/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/sparc64/include/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/v850/include/rtems/score/cpu.h | 2 ++
18 files changed, 45 insertions(+)
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index f5827b4fc6..3f06c036f0 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -165,6 +165,8 @@
/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
#define CPU_STACK_ALIGNMENT 8
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* Bitfield handler macros.
*
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
index a361e023ed..d3e4e4b057 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
@@ -563,6 +563,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 8
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#ifndef ASM
/*
diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
index 84565d15d2..65f28ac435 100644
--- a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
@@ -465,6 +465,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_STACK_ALIGNMENT 8
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/* ISR handler macros */
/*
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
index 0986663be1..226d20b85f 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
@@ -384,6 +384,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define CPU_STACK_ALIGNMENT 16
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/* macros */
#ifndef ASM
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
index fe8107c51b..77f3389f39 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
@@ -581,6 +581,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* ISR handler macros
*/
diff --git a/cpukit/score/cpu/m32c/include/rtems/score/cpu.h
b/cpukit/score/cpu/m32c/include/rtems/score/cpu.h
index c5486e80d6..3f23c21d88 100644
--- a/cpukit/score/cpu/m32c/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m32c/include/rtems/score/cpu.h
@@ -556,6 +556,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 0
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* ISR handler macros
*/
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
index 459ef8a9cd..bd1f29abe4 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
@@ -355,6 +355,8 @@ extern void* _VBR;
#define CPU_STACK_ALIGNMENT 0
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#ifndef ASM
/* macros */
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpu.h
b/cpukit/score/cpu/mips/include/rtems/score/cpu.h
index 46d1eb28e8..c20e5f4f01 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpu.h
@@ -631,6 +631,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
void mips_vector_exceptions( CPU_Interrupt_frame *frame );
/*
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
index 403b05f9fb..9b6dbecc9c 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpu.h
@@ -465,6 +465,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 0
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* ISR handler macros
*/
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
b/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
index 1d088ed058..3cc56e591b 100644
--- a/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/nios2/include/rtems/score/cpu.h
@@ -87,6 +87,8 @@ extern "C" {
*/
#define CPU_STACK_ALIGNMENT 4
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* A Nios II configuration with an external interrupt controller (EIC) supports
* up to 64 interrupt levels. A Nios II configuration with an internal
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
index acb6356efa..ba6e7fe02a 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
@@ -695,6 +695,14 @@ extern Context_Control_fp _CPU_Null_fp_context;
*/
#define CPU_STACK_ALIGNMENT 0
+/**
+ * The alignment of the interrupt stack in bytes.
+ *
+ * The alignment should take the stack ABI and the cache line size into
+ * account.
+ */
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* ISR handler macros
*/
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
index b13057712a..b9296df6e1 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
@@ -462,6 +462,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_STACK_ALIGNMENT 0
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/* ISR handler macros */
/*
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
index db2479b210..ac6ecccc1d 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
@@ -762,6 +762,8 @@ void ppc_set_interrupt_level( uint32_t level );
#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT)
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#ifndef ASM
/* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index c073006cb1..ad2d3dbe46 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -137,6 +137,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_CONTEXT_FP_SIZE 0
Context_Control_fp _CPU_Null_fp_context;
+#define CPU_CACHE_LINE_BYTES 64
+
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#if __riscv_xlen == 32
#define CPU_STACK_MINIMUM_SIZE 4096
@@ -148,6 +150,9 @@ Context_Control_fp _CPU_Null_fp_context;
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
#define CPU_STACK_ALIGNMENT 8
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#define _CPU_Initialize_vectors()
/*
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h
b/cpukit/score/cpu/sh/include/rtems/score/cpu.h
index 79453bc1ac..d3c9bc6d39 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpu.h
@@ -438,6 +438,8 @@ void CPU_delay( uint32_t microseconds );
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* ISR handler macros
*/
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
index 55c1387aaa..8aa701dde2 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/include/rtems/score/cpu.h
@@ -823,6 +823,8 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#ifndef ASM
/*
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
index f1412e0bbb..feb7752915 100644
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
@@ -709,6 +709,8 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define CPU_STACK_ALIGNMENT 16
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#ifndef ASM
/*
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpu.h
b/cpukit/score/cpu/v850/include/rtems/score/cpu.h
index 5c65f8532f..dbae3c4234 100644
--- a/cpukit/score/cpu/v850/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/v850/include/rtems/score/cpu.h
@@ -524,6 +524,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 4
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
/*
* ISR handler macros
*/
--
2.13.7
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