On 20/03/2018 18:10, Amaan Cheval wrote: > On Tue, Mar 20, 2018 at 11:44 AM Chris Johns <chr...@rtems.org> wrote: >> On 20/03/2018 16:21, Amaan Cheval wrote: >>> On Tue, Mar 20, 2018 at 8:23 AM Chris Johns <chr...@rtems.org> wrote: >>>> On 19/03/2018 18:36, Amaan Cheval wrote: >>> (Assuming that by tables you meant the Local Vector Table, etc., and not >>> the ACPI's MADT, which is relevant to SMP in that it contains a list of >>> LAPICs, thereby letting us find how many cores are available.) > >> I was thinking about the SMP tables. SMP is not part of this work at the > moment >> so what ever is needed in this area to make the BSP work. Is the Local > Vector >> Table included in the list of tables? > > Oh, did you mean the MP Table / ACPI MADT as mentioned in the 2nd bullet > here? (From volume 3 of Intel's IA32 and 64 manual.) > https://i.imgur.com/elZIlfy.png
It has been a while since I looked at this. Is there a table for interrupts and interrupts beyond the master/slave legacy PICs? > One of those tables will need to be parsed to configure boot for SMP > systems correctly, yes. I thought you meant the tables that need to be > setup for the local APIC to be initialized and used correctly (which is > also necessary to be able to send Startup Inter-Proessor Interrupts (SIPI) > for SMP boot to work). I think interrupts to access to various PCI devices beyond the slave PIC is all we need for now. Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
