From: Hesham Almatary <hes...@alumni.york.ac.uk> * Only runs/tested on simulator/spike. * Ticker, hello, capture work proprely * Tested via RTEMS Tester, Passed: 525/565 (92%) --- c/src/lib/libbsp/riscv32/Makefile.am | 14 + c/src/lib/libbsp/riscv32/acinclude.m4 | 10 + c/src/lib/libbsp/riscv32/configure.ac | 19 ++ c/src/lib/libbsp/riscv32/riscv_generic/Makefile.am | 93 +++++ c/src/lib/libbsp/riscv32/riscv_generic/bsp_specs | 13 + .../libbsp/riscv32/riscv_generic/clock/clockdrv.c | 114 +++++++ .../lib/libbsp/riscv32/riscv_generic/configure.ac | 36 ++ .../riscv32/riscv_generic/console/console-io.c | 178 ++++++++++ .../lib/libbsp/riscv32/riscv_generic/include/bsp.h | 73 ++++ .../libbsp/riscv32/riscv_generic/include/bspopts.h | 68 ++++ .../lib/libbsp/riscv32/riscv_generic/include/irq.h | 49 +++ .../libbsp/riscv32/riscv_generic/include/tm27.h | 53 +++ c/src/lib/libbsp/riscv32/riscv_generic/irq/irq.c | 65 ++++ .../riscv_generic/make/custom/riscv_generic.cfg | 7 + .../lib/libbsp/riscv32/riscv_generic/start/start.S | 122 +++++++ .../riscv32/riscv_generic/startup/bsp_fatal_halt.c | 18 + .../libbsp/riscv32/riscv_generic/startup/linkcmds | 378 +++++++++++++++++++++ .../lib/libbsp/riscv32/riscv_generic/timer/timer.c | 70 ++++ .../libbsp/riscv32/shared/include/linker-symbols.h | 81 +++++ 19 files changed, 1461 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/Makefile.am create mode 100644 c/src/lib/libbsp/riscv32/acinclude.m4 create mode 100644 c/src/lib/libbsp/riscv32/configure.ac create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/Makefile.am create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/bsp_specs create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/clock/clockdrv.c create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/configure.ac create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/console/console-io.c create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/include/bsp.h create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/include/bspopts.h create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/include/irq.h create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/include/tm27.h create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/irq/irq.c create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/make/custom/riscv_generic.cfg create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/start/start.S create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/startup/bsp_fatal_halt.c create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/startup/linkcmds create mode 100644 c/src/lib/libbsp/riscv32/riscv_generic/timer/timer.c create mode 100644 c/src/lib/libbsp/riscv32/shared/include/linker-symbols.h
diff --git a/c/src/lib/libbsp/riscv32/Makefile.am b/c/src/lib/libbsp/riscv32/Makefile.am new file mode 100644 index 0000000..9c319b6 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/Makefile.am @@ -0,0 +1,14 @@ +ACLOCAL_AMFLAGS = -I ../../../aclocal +## Descend into the @RTEMS_BSP_FAMILY@ directory +## Currently, the shared directory is not explicitly +## added but it is present in the source tree. + + +_SUBDIRS = @RTEMS_BSP_FAMILY@ + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = shared/include/linker-symbols.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../automake/subdirs.am +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libbsp/riscv32/acinclude.m4 b/c/src/lib/libbsp/riscv32/acinclude.m4 new file mode 100644 index 0000000..2358993 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/acinclude.m4 @@ -0,0 +1,10 @@ +# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY) +AC_DEFUN([RTEMS_CHECK_BSPDIR], +[ + case "$1" in + riscv_generic ) + AC_CONFIG_SUBDIRS([riscv_generic]);; + *) + AC_MSG_ERROR([Invalid BSP]);; + esac +]) diff --git a/c/src/lib/libbsp/riscv32/configure.ac b/c/src/lib/libbsp/riscv32/configure.ac new file mode 100644 index 0000000..116fa2f --- /dev/null +++ b/c/src/lib/libbsp/riscv32/configure.ac @@ -0,0 +1,19 @@ +# Process this file with autoconf to produce a configure script. + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-riscv32],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([../riscv32]) +RTEMS_TOP(../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2]) +AM_MAINTAINER_MODE + +RTEMS_ENV_RTEMSBSP +RTEMS_PROJECT_ROOT + +RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY]) + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/Makefile.am b/c/src/lib/libbsp/riscv32/riscv_generic/Makefile.am new file mode 100644 index 0000000..83257ac --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/Makefile.am @@ -0,0 +1,93 @@ +## +# +# @brief Makefile of LibBSP for the RISCV/Spike simulator. +# +# +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am + +include_bspdir = $(includedir)/bsp +include_libcpudir = $(includedir)/libcpu + +dist_project_lib_DATA = bsp_specs + +############################################################################### +# Header # +############################################################################### + +include_HEADERS = include/bsp.h +include_HEADERS += ../../shared/include/tm27.h +include_HEADERS += ../../shared/include/coverhd.h + +nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h +include_bsp_HEADERS = ../shared/include/linker-symbols.h + +include_bsp_HEADERS += ../../../libbsp/shared/include/mm.h +include_bsp_HEADERS += ../../shared/include/utility.h +include_bsp_HEADERS += ../../shared/include/irq-generic.h +include_bsp_HEADERS += ../../shared/include/irq-info.h +include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/include/console-polled.h +include_bsp_HEADERS += include/irq.h + +nodist_include_HEADERS = include/bspopts.h + +############################################################################### +# Data # +############################################################################### +noinst_LIBRARIES = libbspstart.a + +libbspstart_a_SOURCES = start/start.S + +project_lib_DATA = start.$(OBJEXT) + +project_lib_DATA += startup/linkcmds + +############################################################################### +# LibBSP # +############################################################################### + +noinst_LIBRARIES += libbsp.a + +# Startup +libbsp_a_SOURCES = ../../shared/bspreset.c +libbsp_a_SOURCES += ../../shared/bspstart.c +libbsp_a_SOURCES += startup/bsp_fatal_halt.c + +# Shared +libbsp_a_SOURCES += ../../shared/bootcard.c +libbsp_a_SOURCES += ../../shared/bspclean.c +libbsp_a_SOURCES += ../../shared/bsppredriverhook.c +libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c +libbsp_a_SOURCES += ../../shared/sbrk.c +libbsp_a_SOURCES += ../../shared/src/stackalloc.c +libbsp_a_SOURCES += ../../shared/bspgetworkarea.c + +# clock +libbsp_a_SOURCES += clock/clockdrv.c ../../../shared/clockdrv_shell.h + +# Timer +libbsp_a_SOURCES += timer/timer.c + +# console +libbsp_a_SOURCES += ../../shared/console-polled.c + +# IRQ +libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c +libbsp_a_SOURCES += ../../shared/src/irq-generic.c +libbsp_a_SOURCES += ../../shared/src/irq-info.c +libbsp_a_SOURCES += irq/irq.c + +# Cache +libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../../shared/include/cache_.h +libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include + +# debugio +libbsp_a_SOURCES += console/console-io.c + +DISTCLEANFILES = include/bspopts.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/bsp_specs b/c/src/lib/libbsp/riscv32/riscv_generic/bsp_specs new file mode 100644 index 0000000..32c105f --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} + +*endfile: +%{!qrtems: %(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s } diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/clock/clockdrv.c b/c/src/lib/libbsp/riscv32/riscv_generic/clock/clockdrv.c new file mode 100644 index 0000000..f2fc235 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/clock/clockdrv.c @@ -0,0 +1,114 @@ +/** + * @file + * + * @ingroup bsp_clock + * + * @brief riscv clock support. + */ + +/* + * riscv_generic Clock driver + * + * COPYRIGHT (c) 2015 Hesham Alatary <hes...@alumni.york.ac.uk> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE + */ + +#include <rtems.h> +#include <bsp.h> +#include <bsp/irq.h> +#include <rtems/score/riscv-utility.h> +#include <rtems/score/cpu.h> +#include <rtems/timecounter.h> + +/* The number of clock cycles before generating a tick timer interrupt. */ +#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 1000 +#define RISCV_CLOCK_CYCLE_TIME_NANOSECONDS 1 + +static struct timecounter riscv_generic_tc; + +/* CPU counter */ +static CPU_Counter_ticks cpu_counter_ticks; + +/* This prototype is added here to Avoid warnings */ +void Clock_isr(void *arg); + +static void riscv_generic_clock_at_tick(void) +{ + REG(MTIME_MM) = 0; + REG(MTIMECMP_MM) = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; + + cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * 10000; +} + +static void riscv_generic_clock_handler_install(proc_ptr new_isr) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + _CPU_ISR_install_vector(RISCV_MACHINE_TIMER_INTERRUPT, + new_isr, + NULL); + + if (sc != RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +static uint32_t riscv_generic_get_timecount(struct timecounter *tc) +{ + uint32_t ticks_since_last_timer_interrupt = REG(MTIME_MM); + + return cpu_counter_ticks + ticks_since_last_timer_interrupt; +} + +CPU_Counter_ticks _CPU_Counter_read(void) +{ + return riscv_generic_get_timecount(NULL); +} + +static void riscv_generic_clock_initialize(void) +{ + uint32_t mtimecmp = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; + uint64_t frequency = (1000000000 / RISCV_CLOCK_CYCLE_TIME_NANOSECONDS); + + REG(MTIME_MM) = 0; + REG(MTIMECMP_MM) = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; + + /* Enable mtimer interrupts */ + set_csr(mie, MIP_MTIP); + set_csr(mip, MIP_MTIP); + + /* Initialize timecounter */ + riscv_generic_tc.tc_get_timecount = riscv_generic_get_timecount; + riscv_generic_tc.tc_counter_mask = 0xffffffff; + riscv_generic_tc.tc_frequency = frequency; + riscv_generic_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; + rtems_timecounter_install(&riscv_generic_tc); +} + +static void riscv_generic_clock_cleanup(void) +{ + /* Disable mtimer interrupts */ + clear_csr(mie, MIP_MTIP); + clear_csr(mip, MIP_MTIP); +} + +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#define Clock_driver_support_at_tick() riscv_generic_clock_at_tick() + +#define Clock_driver_support_initialize_hardware() riscv_generic_clock_initialize() + +#define Clock_driver_support_install_isr(isr) \ + riscv_generic_clock_handler_install(isr) + +#define Clock_driver_support_shutdown_hardware() riscv_generic_clock_cleanup() + +#include "../../../shared/clockdrv_shell.h" diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/configure.ac b/c/src/lib/libbsp/riscv32/riscv_generic/configure.ac new file mode 100644 index 0000000..92c1b96 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/configure.ac @@ -0,0 +1,36 @@ +## +# +# @file +# +# @brief Configure script of LibBSP for riscv_generic BSP. +# + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-riscv_generic],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + +RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP +start]) + +RTEMS_BSPOPTS_SET([BSP_RISCV32_PERIPHCLK],[*],[100000000U]) +RTEMS_BSPOPTS_HELP([BSP_RISCV32_PERIPHCLK],[riscv PERIPHCLK clock +frequency in Hz]) + +RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]) +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_CHECK_SMP +AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) + +RTEMS_BSP_CLEANUP_OPTIONS(0, 1) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/console/console-io.c b/c/src/lib/libbsp/riscv32/riscv_generic/console/console-io.c new file mode 100644 index 0000000..8e03b99 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/console/console-io.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/console-polled.h> +#include <rtems/libio.h> +#include <stdlib.h> +#include <assert.h> +#include <stdio.h> + +/* Most of the code below is copied from riscv-pk project */ +# define TOHOST_CMD(dev, cmd, payload) \ + (((uint64_t)(dev) << 56) | ((uint64_t)(cmd) << 48) | (uint64_t)(payload)) + +#define FROMHOST_DEV(fromhost_value) ((uint64_t)(fromhost_value) >> 56) +#define FROMHOST_CMD(fromhost_value) ((uint64_t)(fromhost_value) << 8 >> 56) +#define FROMHOST_DATA(fromhost_value) ((uint64_t)(fromhost_value) << 16 >> 16) + +volatile uint64_t tohost __attribute__((section(".htif"))); +volatile uint64_t fromhost __attribute__((section(".htif"))); +volatile int htif_console_buf; + +static void __check_fromhost() +{ + uint64_t fh = fromhost; + if (!fh) { + return; + } + fromhost = 0; + + // this should be from the console + assert(FROMHOST_DEV(fh) == 1); + switch (FROMHOST_CMD(fh)) { + case 0: + htif_console_buf = 1 + (uint8_t)FROMHOST_DATA(fh); + break; + case 1: + break; + default: + assert(0); + } +} + +static void __set_tohost(uintptr_t dev, uintptr_t cmd, uintptr_t data) +{ + while (tohost) { + __check_fromhost(); + } + tohost = TOHOST_CMD(dev, cmd, data); +} + +int htif_console_getchar() +{ + __check_fromhost(); + int ch = htif_console_buf; + if (ch >= 0) { + htif_console_buf = -1; + __set_tohost(1, 0, 0); + } + + return ch - 1; +} + +static void do_tohost_fromhost(uintptr_t dev, uintptr_t cmd, uintptr_t data) +{ + __set_tohost(dev, cmd, data); + + while (1) { + uint64_t fh = fromhost; + if (fh) { + if (FROMHOST_DEV(fh) == dev && FROMHOST_CMD(fh) == cmd) { + fromhost = 0; + break; + } + __check_fromhost(); + } + } +} + +void htif_console_putchar(uint8_t ch) +{ + __set_tohost(1, 1, ch); +} + +void htif_poweroff() +{ + while (1) { + fromhost = 0; + tohost = 1; + } +} + +void console_initialize_hardware(void) +{ + /* Do nothing */ +} + +static void outbyte_console(char ch) +{ + htif_console_putchar(ch); + return 0; +} + +static char inbyte_console(void) +{ + return htif_console_getchar(); +} + +/* + * console_outbyte_polled + * + * This routine transmits a character using polling. + */ +void console_outbyte_polled( + int port, + char ch +) +{ + outbyte_console( ch ); +} + +/* + * console_inbyte_nonblocking + * + * This routine polls for a character. + */ + +int console_inbyte_nonblocking(int port) +{ + char c; + + c = inbyte_console(); + if (!c) { + return -1; + } + return (int) c; +} + +/* + * To support printk + */ + +#include <rtems/bspIo.h> + +static void RISCV_output_char(char c) +{ + console_outbyte_polled( 0, c ); +} + +BSP_output_char_function_type BSP_output_char = RISCV_output_char; +BSP_polling_getchar_function_type BSP_poll_char = + (void *)console_inbyte_nonblocking; diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/include/bsp.h b/c/src/lib/libbsp/riscv32/riscv_generic/include/bsp.h new file mode 100644 index 0000000..99fe958 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/include/bsp.h @@ -0,0 +1,73 @@ +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_GENERIC_H +#define LIBBSP_RISCV_GENERIC_H + +#include <rtems.h> +#include <rtems/clockdrv.h> +#include <rtems/console.h> + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems/devnull.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup riscv_generic Register Definitions + * + * @ingroup riscv_generic + * + * @brief Shared register definitions for RISC-V systems. + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + +#define REG(x) (*((volatile uint32_t *) (x))) +#define BIT(n) (1 << (n)) + +#define MTIME_MM 0x0200bff8 +#define MTIMECMP_MM 0x02004000 + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_RISCV_GENERIC_H */ diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/include/bspopts.h b/c/src/lib/libbsp/riscv32/riscv_generic/include/bspopts.h new file mode 100644 index 0000000..7858ce0 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/include/bspopts.h @@ -0,0 +1,68 @@ +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* include/bspopts.h.in. Generated from configure.ac by autoheader. */ + +/* If defined, then the BSP Framework will put a non-zero pattern into the + RTEMS Workspace and C program heap. This should assist in finding code that + assumes memory starts set to zero. */ +#undef BSP_DIRTY_MEMORY + +/* If defined, print a message and wait until pressed before resetting board + when application exits. */ +#undef BSP_PRESS_KEY_FOR_RESET + +/* If defined, prints the exception context when an unexpected exception + occurs. */ +#undef BSP_PRINT_EXCEPTION_CONTEXT + +/* If defined, reset the board when the application exits. */ +#undef BSP_RESET_BOARD_AT_EXIT + +/* reset vector address for BSP start */ +#undef BSP_START_RESET_VECTOR + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/include/irq.h b/c/src/lib/libbsp/riscv32/riscv_generic/include/irq.h new file mode 100644 index 0000000..d7ee45b --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/include/irq.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup RISCV_IRQ + * + * @brief Interrupt definitions. + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_GENERIC_RISCV_IRQ_H +#define LIBBSP_GENERIC_RISCV_IRQ_H + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#define BSP_INTERRUPT_VECTOR_MIN 0x0 +#define BSP_INTERRUPT_VECTOR_MAX 0x24 + +#endif /* ASM */ +#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/include/tm27.h b/c/src/lib/libbsp/riscv32/riscv_generic/include/tm27.h new file mode 100644 index 0000000..392f106 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/include/tm27.h @@ -0,0 +1,53 @@ +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @name Interrupt mechanisms for Time Test 27 + * @{ + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) /* empty */ + +#define Cause_tm27_intr() /* empty */ + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/irq/irq.c b/c/src/lib/libbsp/riscv32/riscv_generic/irq/irq.c new file mode 100644 index 0000000..af6e08e --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/irq/irq.c @@ -0,0 +1,65 @@ +/** + * @file + * + * @ingroup riscv_interrupt + * + * @brief Interrupt support. + */ + +/* + * RISCV CPU Dependent Source + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <bsp/irq.h> +#include <bsp/irq-generic.h> + +/* Almost all of the jobs that the following functions should + * do are implemented in cpukit + */ + +void bsp_interrupt_handler_default(rtems_vector_number vector) +{ + printk("spurious interrupt: %u\n", vector); +} + +rtems_status_code bsp_interrupt_facility_initialize() +{ + /* TODO */ + return 0; +} + +void bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + /* TODO */ + return 0; +} + +void bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + /* TODO */ + return 0; +} diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/make/custom/riscv_generic.cfg b/c/src/lib/libbsp/riscv32/riscv_generic/make/custom/riscv_generic.cfg new file mode 100644 index 0000000..a7f46c7 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/make/custom/riscv_generic.cfg @@ -0,0 +1,7 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv32 + +CPU_CFLAGS = + +CFLAGS_OPTIMIZE_V ?= -O0 -g diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/start/start.S b/c/src/lib/libbsp/riscv32/riscv_generic/start/start.S new file mode 100644 index 0000000..692afe5 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/start/start.S @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include <bsp/linker-symbols.h> +#include <rtems/score/riscv-utility.h> +#include <rtems/asm.h> + +# define LREG lw +# define SREG sw + +EXTERN(bsp_section_bss_begin) +EXTERN(bsp_section_bss_end) +EXTERN(ISR_Handler) +EXTERN(bsp_start_vector_table_size) +EXTERN(bsp_vector_table_size) +EXTERN(bsp_section_stack_begin) + +PUBLIC(bsp_start_vector_table_begin) +PUBLIC(bsp_start_vector_table_end) +PUBLIC(_start) + +.section .start, "wax" +TYPE_FUNC(_start) +SYM(_start): + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + la t0, ISR_Handler + csrw mtvec, t0 + + /* load stack and frame pointers */ + la sp, bsp_section_stack_begin + + /* Clearing .bss */ + la t0, bsp_section_bss_begin + la t1, bsp_section_bss_end + +_loop_clear_bss: + bge t0, t1, _end_clear_bss + sw x0, 0(t0) + addi t0, t0, 4 + j _loop_clear_bss +_end_clear_bss: + + /* Init FPU unit if it's there */ + li t0, MSTATUS_FS + csrs mstatus, t0 + + j boot_card + + .align 2 +bsp_start_vector_table_begin: + .word _RISCV_Exception_default /* User int */ + .word _RISCV_Exception_default /* Supervisor int */ + .word _RISCV_Exception_default /* Reserved */ + .word _RISCV_Exception_default /* Machine int */ + .word _RISCV_Exception_default /* User timer int */ + .word _RISCV_Exception_default /* Supervisor Timer int */ + .word _RISCV_Exception_default /* Reserved */ + .word _RISCV_Exception_default /* Machine Timer int */ + .word _RISCV_Exception_default /* User external int */ + .word _RISCV_Exception_default /* Supervisor external int */ + .word _RISCV_Exception_default /* Reserved */ + .word _RISCV_Exception_default /* Machine external int */ + .word _RISCV_Exception_default + .word _RISCV_Exception_default + .word _RISCV_Exception_default + .word _RISCV_Exception_default +bsp_start_vector_table_end: diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/startup/bsp_fatal_halt.c b/c/src/lib/libbsp/riscv32/riscv_generic/startup/bsp_fatal_halt.c new file mode 100644 index 0000000..e918c13 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/startup/bsp_fatal_halt.c @@ -0,0 +1,18 @@ +/* @ingroup riscv_generic + * @brief riscv_generic BSP Fatal_halt handler. + * + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp.h> + +/* Send a power-off signal to the host */ +void _CPU_Fatal_halt(uint32_t source, uint32_t error) +{ + htif_poweroff(); +} diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/startup/linkcmds b/c/src/lib/libbsp/riscv32/riscv_generic/startup/linkcmds new file mode 100644 index 0000000..0ed37ad --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/startup/linkcmds @@ -0,0 +1,378 @@ +/** + * @file + * + * @ingroup bsp_linker + * + * @brief Memory map + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham ALMatary <hmka...@york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_ARCH (riscv) + +ENTRY (_start) + +MEMORY +{ + RAM : ORIGIN = 0x0000000080000000, LENGTH = 0x10000000 +} + +REGION_ALIAS ("REGION_VECTOR", RAM); +REGION_ALIAS ("REGION_START", RAM); +REGION_ALIAS ("REGION_TEXT", RAM); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_RODATA", RAM); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM); +REGION_ALIAS ("REGION_DATA", RAM); +REGION_ALIAS ("REGION_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_HTIF", RAM); +REGION_ALIAS ("REGION_HTIF_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_DATA", RAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_BSS", RAM); +REGION_ALIAS ("REGION_WORK", RAM); +REGION_ALIAS ("REGION_STACK", RAM); + +/* + * Global symbols that may be defined externally + */ +bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? bsp_vector_table_size : 64; + +bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ? bsp_section_xbarrier_align : 1; +bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1; +bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1; + +bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 8; + +bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024; +bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align); + +_bsp_processor_count = DEFINED (_bsp_processor_count) ? _bsp_processor_count : 1; + +SECTIONS { + + .vector : + { + . = ALIGN(8); + bsp_section_vector_begin = .; + *(.vector) + . = ALIGN(bsp_vector_table_size); + bsp_section_vector_end = .; + } > REGION_VECTOR AT > REGION_VECTOR + bsp_section_vector_size = bsp_section_vector_end - bsp_section_vector_begin; + bsp_vector_table_begin = bsp_section_vector_begin; + bsp_vector_table_end = bsp_vector_table_begin + bsp_vector_table_size; + + .start : + { + . = ALIGN(8); + bsp_section_start_begin = .; + KEEP (*(.bsp_start_text)) + KEEP (*(.bsp_start_data)) + bsp_section_start_end = .; + } > REGION_START AT > REGION_START + bsp_section_start_size = bsp_section_start_end - bsp_section_start_begin; + +.xbarrier : { + . = ALIGN (bsp_section_xbarrier_align); + } > REGION_VECTOR AT > REGION_VECTOR + +.text : { + . = ALIGN(8); + bsp_section_text_begin = .; + *(.text.unlikely .text.*_unlikely) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .init : { + KEEP (*(.init)) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .fini : { + KEEP (*(.fini)) + . = ALIGN(8); + bsp_section_text_end = .; + } > REGION_TEXT AT > REGION_TEXT_LOAD + bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; + bsp_section_text_load_begin = LOADADDR (.text); + bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; + +.robarrier : { + . = ALIGN (bsp_section_robarrier_align); + } > REGION_RODATA AT > REGION_RODATA + +.rodata : { + . = ALIGN(8); + bsp_section_rodata_begin = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD +.eh_frame : { + KEEP (*(.eh_frame)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gcc_except_table : { + *(.gcc_except_table .gcc_except_table.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tdata : { + _TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + _TLS_Data_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tbss : { + _TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + _TLS_BSS_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; + _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; + _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; + _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; + _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; + _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + .preinit_array : { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .init_array : { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .fini_array : { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .ctors : { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dtors : { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .data.rel.ro : { + *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) + *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .jcr : { + KEEP (*(.jcr)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .interp : { + *(.interp) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .note.gnu.build-id : { + *(.note.gnu.build-id) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .hash : { + *(.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.hash : { + *(.gnu.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynsym : { + *(.dynsym) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynstr : { + *(.dynstr) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version : { + *(.gnu.version) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_d : { + *(.gnu.version_d) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_r : { + *(.gnu.version_r) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rel.dyn : { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rel_iplt_start = .); + *(.rel.iplt) + PROVIDE_HIDDEN (__rel_iplt_end = .); + PROVIDE_HIDDEN (__rela_iplt_start = .); + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.dyn : { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rel_iplt_start = .); + PROVIDE_HIDDEN (__rel_iplt_end = .); + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rel.plt : { + *(.rel.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.plt : { + *(.rela.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .plt : { + *(.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .iplt : { + *(.iplt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynamic : { + *(.dynamic) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got : { + *(.got.plt) *(.igot.plt) *(.got) *(.igot) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rtemsroset : { + /* Special FreeBSD linker set sections */ + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = .; + *(set_domain_*); + *(set_pseudo_*); + + KEEP (*(SORT(.rtemsroset.*))) + . = ALIGN(8); + bsp_section_rodata_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + bsp_section_rodata_size = bsp_section_rodata_end - bsp_section_rodata_begin; + bsp_section_rodata_load_begin = LOADADDR (.rodata); + bsp_section_rodata_load_end = bsp_section_rodata_load_begin + bsp_section_rodata_size; + + /*--------------------------------------------------------------------*/ + /* HTIF, isolated onto separate page */ + /*--------------------------------------------------------------------*/ + .htif : + { + . = ALIGN(0x1000); + *(.htif) + . = ALIGN(0x1000); + } > REGION_HTIF AT > REGION_HTIF_LOAD + + +.rwbarrier : { + . = ALIGN(8); + . = ALIGN (bsp_section_rwbarrier_align); + } > REGION_DATA AT > REGION_DATA + +.data : { + . = ALIGN(8); + bsp_section_data_begin = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } > REGION_DATA AT > REGION_DATA_LOAD + .data1 : { + *(.data1) + } > REGION_DATA AT > REGION_DATA_LOAD + .rtemsrwset : { + KEEP (*(SORT(.rtemsrwset.*))) + . = ALIGN(8); + bsp_section_data_end = .; + } > REGION_DATA AT > REGION_DATA_LOAD + bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; + bsp_section_data_load_begin = LOADADDR (.data); + bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; + + .bss : { + . = ALIGN(8); + bsp_section_bss_begin = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + bsp_section_bss_end = .; + } > REGION_BSS AT > REGION_BSS + bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; + +.work : { + /* + * The work section will occupy the remaining REGION_WORK region and + * contains the RTEMS work space and heap. + */ + . = ALIGN(8); + bsp_section_work_begin = .; + . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); + . = ALIGN(8); + bsp_section_work_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; + + .stack : { + . = ALIGN(8); + bsp_section_stack_begin = .; + . += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE (.); + . = ALIGN(8); + bsp_section_stack_end = .; + } > REGION_STACK AT > REGION_STACK + bsp_section_stack_size = bsp_section_stack_begin - bsp_section_stack_end; + + RamBase = ORIGIN (REGION_WORK); + RamSize = LENGTH (REGION_WORK); + WorkAreaBase = bsp_section_work_begin; + HeapSize = 0; +} diff --git a/c/src/lib/libbsp/riscv32/riscv_generic/timer/timer.c b/c/src/lib/libbsp/riscv32/riscv_generic/timer/timer.c new file mode 100644 index 0000000..4dd3193 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/riscv_generic/timer/timer.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham Almatary <hes...@alumni.york.ac.uk> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <rtems.h> +#include <bsp.h> +#include <rtems/btimer.h> +#include <rtems/score/riscv-utility.h> + +extern char bsp_start_vector_table_begin[]; + +bool benchmark_timer_find_average_overhead; + +static void benchmark_timer1_interrupt_handler(void) +{ +} + +/* Start eCore tiemr 1 usef for profiling and timing analysis */ +void benchmark_timer_initialize( void ) +{ + /* Install interrupt handler for timer 1 */ +} + +/* + * The following controls the behavior of benchmark_timer_read(). + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ +/* (Y countdowns) to start/stop the timer. */ +/* This value is in microseconds. */ +#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ + +benchmark_timer_t benchmark_timer_read( void ) +{ +} + +void benchmark_timer_disable_subtracting_average_overhead( + bool find_flag +) +{ + benchmark_timer_find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/riscv32/shared/include/linker-symbols.h b/c/src/lib/libbsp/riscv32/shared/include/linker-symbols.h new file mode 100644 index 0000000..a4b03f5 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/shared/include/linker-symbols.h @@ -0,0 +1,81 @@ +#ifndef LIBBSP_RISCV_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_RISCV_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup riscv_linker Linker Support + * + * @ingroup riscv_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM +#define LINKER_SYMBOL(sym) extern char sym []; +#else +#define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +LINKER_SYMBOL(_bsp_processor_count) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_RISCV_SHARED_LINKER_SYMBOLS_H */ -- 2.7.4 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
