On 26/07/17 15:01, Denis Obrezkov wrote:
Hello all,
I have read RTEMS manuals but still can't fully understand how interrupts
are handled.
The manuals will be of no help here.
For example, when an interrupt occurs pc is set to an IRQ handler address.
So, the program's execution continued from that place.
And my question is: how do set_vector and rtems_interrupt_catch relate
to each other and to that IRQ function address installed in a processor
during initialization?
The set_vector() and rtems_interrupt_catch() are legacy functions. They
should not be used for new ports. The set_vector() is not documented.
The rtems_interrupt_catch() lacks important features like an argument
pointer for the handler.
For RISC like machines the ARM
cpukit/score/cpu/arm/arm_exc_interrupt.S
and PowerPC
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S
sources are a good reference. The SPARC is too complicated due to its
register windows. The ARM is also a bit complicated due to the different
processor modes. I would start with a look at the PowerPC code.
In general you do the following:
Save volatile registers
Increment thread dispatch and ISR nest level
Switch to interrupt stack if necessary
Call high level handler (installed via rtems_interrupt_handler_install())
Decrement thread dispatch and ISR nest level
Do a thread dispatch if necessary and allowed
Restore volatile registers
Return from interrupt
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
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Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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