From: Christian Mauderer <christian.maude...@embedded-brains.de>
---
c/src/lib/libbsp/arm/atsam/configure.ac | 12 +++++++-
c/src/lib/libbsp/arm/atsam/startup/ram-config.c | 41 +++++++++++++++++++++++++
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/c/src/lib/libbsp/arm/atsam/configure.ac
b/c/src/lib/libbsp/arm/atsam/configure.ac
index 1297367..83c64b4 100644
--- a/c/src/lib/libbsp/arm/atsam/configure.ac
+++ b/c/src/lib/libbsp/arm/atsam/configure.ac
@@ -50,6 +50,16 @@ AC_ARG_ENABLE(
esac],
[AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ;
INTSRAM=0x00060000])
+AC_ARG_ENABLE(
+[sdram],
+[AS_HELP_STRING([--enable-sdram],[select a SDRAM variant (default
is42s16100e-7bli)])],
+[case "${enableval}" in
+ is42s16100e-7bli) AC_DEFINE([__SDRAM_IS42S16100E_7BLI__],[1],[SDRAM
variant]) EXTSDRAM=0x00200000 ;;
+ is42s16320f-7bl) AC_DEFINE([__SDRAM_IS42S16320F_7BL__],[1],[SDRAM variant])
EXTSDRAM=0x04000000 ;;
+ *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;;
+esac],
+[AC_DEFINE([__SDRAM_IS42S16100E_7BLI__],[1],[SDRAM variant])
EXTSDRAM=0x00200000])
+
RTEMS_BSPOPTS_SET([BOARD_MAINOSC],[*],[12000000])
RTEMS_BSPOPTS_HELP([BOARD_MAINOSC],[Main oscillator frequency in Hz (default
12MHz)])
@@ -76,7 +86,7 @@ AC_ARG_VAR([$1],[$2])dnl
ATSAM_LINKCMD([ATSAM_MEMORY_TCM_SIZE],[size of tightly coupled memories (TCM)
in bytes],[0x00000000])
ATSAM_LINKCMD([ATSAM_MEMORY_INTFLASH_SIZE],[size of internal flash in
bytes],[${INTFLASH}])
ATSAM_LINKCMD([ATSAM_MEMORY_INTSRAM_SIZE],[size of internal SRAM in
bytes],[${INTSRAM}])
-ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in
bytes],[0x00200000])
+ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in
bytes],[${EXTSDRAM}])
ATSAM_LINKCMD([ATSAM_MEMORY_QSPIFLASH_SIZE],[size of QSPI flash in
bytes],[0x00200000])
AC_CONFIG_FILES([
diff --git a/c/src/lib/libbsp/arm/atsam/startup/ram-config.c
b/c/src/lib/libbsp/arm/atsam/startup/ram-config.c
index 65060a7..e957107 100644
--- a/c/src/lib/libbsp/arm/atsam/startup/ram-config.c
+++ b/c/src/lib/libbsp/arm/atsam/startup/ram-config.c
@@ -12,10 +12,13 @@
* http://www.rtems.org/license/LICENSE.
*/
+#include <bspopts.h>
#include <chip.h>
#include <include/board_memories.h>
+#if defined __SDRAM_IS42S16100E_7BLI__
const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
+ /* FIXME: a lot of these values should be calculated using CPU frequency */
.sdramc_tr = 1562,
.sdramc_cr =
SDRAMC_CR_NC_COL8 /* 8 column bits */
@@ -32,3 +35,41 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
.sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
.sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2)
};
+
+#elif defined __SDRAM_IS42S16320F_7BL__
+#define CLOCK_CYCLES_FROM_NS_MAX(ns) \
+ (((ns) * (BOARD_MCK / 1000ul / 1000ul)) / 1000ul)
+#define CLOCK_CYCLES_FROM_NS_MIN(ns) (CLOCK_CYCLES_FROM_NS_MAX(ns) + 1)
+
+const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
+ /* 8k refresh cycles every 64ms => 7.8125us */
+ .sdramc_tr = CLOCK_CYCLES_FROM_NS_MAX(7812ul),
+ .sdramc_cr =
+ SDRAMC_CR_NC_COL10
+ | SDRAMC_CR_NR_ROW13
+ | SDRAMC_CR_CAS_LATENCY3
+ | SDRAMC_CR_NB_BANK4
+ | SDRAMC_CR_DBW
+ /* t_WR = 30ns min (t_RC - t_RP - t_RCD;
+ * see data sheet November 2015 page 55);
+ * add some security margin */
+ | SDRAMC_CR_TWR(CLOCK_CYCLES_FROM_NS_MIN(40))
+ | SDRAMC_CR_TRC_TRFC(CLOCK_CYCLES_FROM_NS_MIN(60))
+ | SDRAMC_CR_TRP(CLOCK_CYCLES_FROM_NS_MIN(15))
+ | SDRAMC_CR_TRCD(CLOCK_CYCLES_FROM_NS_MIN(15))
+ | SDRAMC_CR_TRAS(CLOCK_CYCLES_FROM_NS_MIN(37))
+ | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)),
+ .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
+ .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
+ SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14))
+};
+
+#if CLOCK_CYCLES_FROM_NS_MIN(67) > 0xF
+ /* Prevent the fields to be out of range by checking the one with the biggest
+ * value. */
+ #error SDRAM calculation does not work for the selected clock frequency
+#endif
+
+#else
+ #error SDRAM not supported.
+#endif
--
2.9.3
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