On Jul 4, 2016 8:40 PM, "Alan Cudmore" <alan.cudm...@gmail.com> wrote: > > I figured out my problem with the RPI 2, it was a configuration problem with my build. > > So the latest RTEMS Git builds and runs on Raspberry Pi 2, Raspberry Pi A+, and Raspberry Pi Zero, all with the latest firmware.
How are the drystones? > Thanks, > Alan > > > > > On Jul 4, 2016, at 6:29 PM, Alan Cudmore <alan.cudm...@gmail.com> wrote: > > > > I updated my RTEMS git and rebuilt the Pi and Pi2 BSPs. > > Pi 1 works, but Pi 2 does not boot. > > > > Pi 1 has a speed up on the dhrystone command: > > I get 90000 dhrystones per second. > > > > When I run your github pi branch, the Pi2 works with both the new and old firmware. > > The new firmware Pi 2 dhrystone command is 26315 dhrystones per second > > The old firmware Pi 2 dhrystone command is 45454 dhrystones per second. > > So something in the firmware and caches is different, I can double check the configuration. > > > > But first, I will have to try to figure out the differences between the RTEMS git and your github and see why the Pi 2 is not booting for me. > > > > Thanks, > > Alan > > > > > >> On Jul 4, 2016, at 4:17 PM, Pavel Pisa <p...@cmp.felk.cvut.cz> wrote: > >> > >> Hello Alan and Rohini Kulkarni, > >> > >> On Monday 04 of July 2016 18:47:09 Alan Cudmore wrote: > >>> Hi Pavel, > >>> I can confirm that your rtems-rpi-devel branch from your github account > >>> works on the Raspberry Pi A+, Raspberry Pi Zero, and Raspberry Pi 2 with > >>> the latest firmware. > >>> > >>> I did notice that the Dhrystone benchmark runs 3 times faster on the Pi 1 > >>> than the Pi 2, but that could be the cache configuration. > >> > >> Is this problem of the new firmware only? > >> If answer is yes, then it can be problem with providing > >> permission to control cache from SVC mode. Then some > >> register setup before switching from HYP mode could be required. > >> > >> If it is not related to new hardware then I think that > >> there is no change in caching attributes introduced > >> by all my changes and experience of Rohini Kulkarni working > >> on RPi2 SMP project in frame of GSoC 2015 could help. > >> Code is on GitHub, > >> > >> https://github.com/krohini1593/rtems > >> > >> which is not merged to RTEMS mainline yet. > >> > >> There are some changes to change cache configuration. > >> > >> I have tried some changes in bsp_start_hook_1 > >> > >> +#include <bsp/arm-cp15-start.h> > >> > >> > >> - bsp_memory_management_initialize(); > >> + uint32_t ctrl; > >> > >> + /* turn mmu off first in case it's on */ > >> + ctrl = arm_cp15_start_setup_mmu_and_cache( > >> + ARM_CP15_CTRL_M | ARM_CP15_CTRL_A, /* clear - mmu off */ > >> + ARM_CP15_CTRL_AFE > >> + ); > >> + > >> + ctrl |= ARM_CP15_CTRL_Z; > >> + > >> + arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( > >> + ctrl, > >> + (uint32_t *) bsp_translation_table_base, > >> + ARM_MMU_DEFAULT_CLIENT_DOMAIN, > >> + &arm_cp15_start_mmu_config_table[0], > >> + arm_cp15_start_mmu_config_table_size > >> + ); > >> > >> to ensure that ARM_CP15_CTRL_Z is set for branch predictor. > >> But I have tried some modifications in BSP and I have observed > >> no changes. RPi1 seems to run about 4 times faster in my case. > >> > >> So it is probable that at cache is not enabled. May be only L2??? > >> > >> There can be mitchmatch between configured MMU table format/bit use > >> and the way bits are filled. I have not time to recheck that > >> yet but RPi2 code matches Cyclone Cortex-A9 BSP in CPU setup > >> so it should be OK if there is not some Broadcom specific control > >> register. > >> > >> Best wishes, > >> > >> Pavel > > > > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel
_______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel