On Sat, Feb 20, 2016 at 11:01 PM, <jakob.viket...@gmail.com> wrote:
> From: Jakob Viketoft <jakob.viket...@aacmicrotec.com>
>
> Close #2602
> ---
> c/src/lib/libcpu/or1k/shared/cache/cache.c | 129
> +++++++++++++++++++++--------
> 1 file changed, 94 insertions(+), 35 deletions(-)
>
> diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c
> b/c/src/lib/libcpu/or1k/shared/cache/cache.c
> index d17fec2..02e4aab 100644
> --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
> +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
> @@ -4,9 +4,14 @@
> * COPYRIGHT (c) 1989-2006
> * On-Line Applications Research Corporation (OAR).
> *
> + * Copyright (c) 2014 ÅAC Microtec AB <www.aacmicrotec.com>
> + * Contributor(s):
> + * Karol Gugala <kgug...@antmicro.com>
> + *
> * The license and distribution terms for this file may be
> * found in the file LICENSE in this distribution or at
> * http://www.rtems.org/license/LICENSE.
> + *
> */
>
> #include <rtems/score/cpu.h>
> @@ -14,13 +19,15 @@
> #include <rtems/score/or1k-utility.h>
> #include <rtems/score/percpu.h>
> #include <libcpu/cache.h>
> +#include <cache_.h>
>
> static inline void _CPU_OR1K_Cache_enable_data(void)
> {
> uint32_t sr;
> - ISR_Level level;
> + ISR_Level level;
>
> _ISR_Disable (level);
> +
> sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
> _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
>
> @@ -30,7 +37,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
> static inline void _CPU_OR1K_Cache_disable_data(void)
> {
> uint32_t sr;
> - ISR_Level level;
> + ISR_Level level;
>
> _ISR_Disable (level);
>
> @@ -43,7 +50,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
> static inline void _CPU_OR1K_Cache_enable_instruction(void)
> {
> uint32_t sr;
> - ISR_Level level;
> + ISR_Level level;
>
> _ISR_Disable (level);
>
> @@ -66,95 +73,109 @@ static inline void
> _CPU_OR1K_Cache_disable_instruction(void)
> _ISR_Enable(level);
> }
>
> -static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
> +static inline void _CPU_OR1K_Cache_data_block_prefetch
> +(const uintptr_t d_addr)
This definition conflicts with the prototype at
libcpu/include/cache.h. It produces a compilation error
> {
> ISR_Level level;
>
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr);
>
> _ISR_Enable(level);
> }
>
> -static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
> +static inline void _CPU_OR1K_Cache_data_block_flush
> +(const uintptr_t d_addr)
ditto
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr);
>
> _ISR_Enable(level);
> }
>
> -static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
> +static inline void _CPU_OR1K_Cache_data_block_invalidate
> +(const uintptr_t d_addr)
ditto
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr);
>
> _ISR_Enable(level);
> }
>
> -static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
> +static inline void _CPU_OR1K_Cache_data_block_writeback
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr);
>
> _ISR_Enable(level);
> }
>
> -static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
> +static inline void _CPU_OR1K_Cache_data_block_lock
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr);
>
> _ISR_Enable(level);
> }
>
> static inline void _CPU_OR1K_Cache_instruction_block_prefetch
> -(const void *d_addr)
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr);
>
> _ISR_Enable(level);
> }
>
> static inline void _CPU_OR1K_Cache_instruction_block_invalidate
> -(const void *d_addr)
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr);
>
> _ISR_Enable(level);
> }
>
> static inline void _CPU_OR1K_Cache_instruction_block_lock
> -(const void *d_addr)
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> - _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
> + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr);
>
> _ISR_Enable(level);
> }
>
> /* Implement RTEMS cache manager functions */
>
> -void _CPU_cache_flush_1_data_line(const void *d_addr)
> +void _CPU_cache_flush_1_data_line
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> _CPU_OR1K_Cache_data_block_flush(d_addr);
> @@ -164,9 +185,11 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
> _ISR_Enable(level);
> }
>
> -void _CPU_cache_invalidate_1_data_line(const void *d_addr)
> +void _CPU_cache_invalidate_1_data_line
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> _CPU_OR1K_Cache_data_block_invalidate(d_addr);
> @@ -184,9 +207,11 @@ void _CPU_cache_unfreeze_data(void)
> /* Do nothing */
> }
>
> -void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
> +void _CPU_cache_invalidate_1_instruction_line
> +(const uintptr_t d_addr)
> {
> - ISR_Level level;
> + ISR_Level level;
> +
> _ISR_Disable (level);
>
> _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
> @@ -206,17 +231,51 @@ void _CPU_cache_unfreeze_instruction(void)
>
> void _CPU_cache_flush_entire_data(void)
> {
> -
> + int addr;
> +
> + /* We have only 0 level cache so we do not need to invalidate others */
> + for (
> + addr = _CPU_cache_get_data_cache_size(0);
> + addr > 0;
> + addr -= CPU_DATA_CACHE_ALIGNMENT
> + ) {
> + _CPU_OR1K_Cache_data_block_flush((void*) addr);
> + }
> }
>
> void _CPU_cache_invalidate_entire_data(void)
> {
> -
> + int addr;
> +
> + /* We have only 0 level cache so we do not need to invalidate others */
> + for (
> + addr = _CPU_cache_get_data_cache_size(0);
> + addr > 0;
> + addr -= CPU_DATA_CACHE_ALIGNMENT
> + ) {
> + _CPU_cache_invalidate_1_data_line((void*) addr);
> + }
> }
>
> void _CPU_cache_invalidate_entire_instruction(void)
> {
> -
> + int addr;
> +
> + /* We have only 0 level cache so we do not need to invalidate others */
> + for (
> + addr = _CPU_cache_get_instruction_cache_size(0);
> + addr > 0;
> + addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT
> + ) {
> + _CPU_cache_invalidate_1_instruction_line((void*) addr);
> + }
> +
> + /* Flush instructions out of instruction buffer */
> + asm volatile("l.nop");
> + asm volatile("l.nop");
> + asm volatile("l.nop");
> + asm volatile("l.nop");
> + asm volatile("l.nop");
> }
>
> void _CPU_cache_enable_data(void)
> --
> 2.1.4
>
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> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
--
Hesham
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