On 4/7/2015 1:57 PM, Cudmore, Alan P. (GSFC-5820) wrote: > We are developing a processor card that has two CPUs on a board with > either a shared memory or FIFO interface between them. Either interface > will have the ability to interrupt the CPU upon receipt of data. > > Is either one more suitable for the RTEMS Multi-Processor interface? Theoretically both are within the design but the shared memory is easier. There is a driver for this now in the tree. You just need to define shm locking instructions.
> Are there any problems or inefficiencies with the MP interface on > SPARC/LEON3? One of the CPUs will be dual core. We have never run an SMP system as a node on a distributed MP configuration. But it should work. AFAIK it hasn't even been built as a configuration yet. > Is there a BSP with an example of a Multi-Processor interface > implementation? leon3 and psim. FWIW there is a subset of the Classic API available on distributed MP configurations. If this isn't enough, that set can be expanded. > Thanks, > Alan > > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.com On-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available (256) 722-9985 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
