Looks good. Please apply it.
danielh
On 03/25/2015 11:42 AM, Sebastian Huber wrote:
---
cpukit/score/cpu/sparc/rtems/score/sparc.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h
b/cpukit/score/cpu/sparc/rtems/score/sparc.h
index ac8c510..45df6ff 100644
--- a/cpukit/score/cpu/sparc/rtems/score/sparc.h
+++ b/cpukit/score/cpu/sparc/rtems/score/sparc.h
@@ -320,7 +320,14 @@ static inline uint32_t sparc_disable_interrupts(void)
static inline void sparc_enable_interrupts(uint32_t psr)
{
register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */
- __asm__ volatile ( "ta %0\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
+
+ /*
+ * The trap instruction has a higher trap priority than the interrupts
+ * according to "The SPARC Architecture Manual: Version 8", Table 7-1
+ * "Exception and Interrupt Request Priority and tt Values". Add a nop to
+ * prevent a trap instruction right after the interrupt enable trap.
+ */
+ __asm__ volatile ( "ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
}
/**
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