I pushed this. You had the right idea to prod us. There is a lot
of code flying right now and we want to not forget any of it.
Some comments.
+ Turn list of implementations into a bullet list with URLs.
+ I turned on spell check in gvim and fixed some.
If someone thinks there are other topics to address, please
speak up.
Is Thread Local Storage supported? I recall we turned it on
in gcc.
--joel
On 8/16/2014 11:30 AM, Hesham ALMatary wrote:
> ---
> doc/cpu_supplement/Makefile.am | 6 +++
> doc/cpu_supplement/cpu_supplement.texi | 2 +
> doc/cpu_supplement/or1k.t | 78
> ++++++++++++++++++++++++++++++++++
> 3 files changed, 86 insertions(+)
> create mode 100644 doc/cpu_supplement/or1k.t
>
> diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
> index 3083922..300ff78 100644
> --- a/doc/cpu_supplement/Makefile.am
> +++ b/doc/cpu_supplement/Makefile.am
> @@ -23,6 +23,7 @@ GENERATED_FILES += m32r.texi
> GENERATED_FILES += m68k.texi
> GENERATED_FILES += microblaze.texi
> GENERATED_FILES += mips.texi
> +GENERATED_FILES += or1k.texi
> GENERATED_FILES += powerpc.texi
> GENERATED_FILES += nios2.texi
> GENERATED_FILES += sh.texi
> @@ -101,6 +102,11 @@ mips.texi: mips.t
> -u "Top" \
> -n "" < $< > $@
>
> +or1k.texi: or1k.t
> + $(BMENU2) -p "" \
> + -u "Top" \
> + -n "" < $< > $@
> +
> powerpc.texi: powerpc.t
> $(BMENU2) -p "" \
> -u "Top" \
> diff --git a/doc/cpu_supplement/cpu_supplement.texi
> b/doc/cpu_supplement/cpu_supplement.texi
> index 1087538..5c484d0 100644
> --- a/doc/cpu_supplement/cpu_supplement.texi
> +++ b/doc/cpu_supplement/cpu_supplement.texi
> @@ -73,6 +73,7 @@
> * M68xxx and Coldfire Specific Information::
> * Xilinx MicroBlaze Specific Information::
> * MIPS Specific Information::
> +* OpenRISC 1000 Specific Information::
> * Altera Nios II Specific Information::
> * PowerPC Specific Information::
> * SuperH Specific Information::
> @@ -97,6 +98,7 @@
> @include microblaze.texi
> @include mips.texi
> @include nios2.texi
> +@include or1k.texi
> @include powerpc.texi
> @include sh.texi
> @include sparc.texi
> diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t
> new file mode 100644
> index 0000000..219f23b
> --- /dev/null
> +++ b/doc/cpu_supplement/or1k.t
> @@ -0,0 +1,78 @@
> +@c
> +@c COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmat...@gmail.com>
> +@c All rights reserved.
> +
> +@ifinfo
> +@end ifinfo
> +@chapter OpenRISC 1000 Specific Information
> +
> +This chapter discusses the
> +@uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture}
> +dependencies in this port of RTEMS. There are many implementations
> +for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic
> +features that all implementations should have.
> +
> +@subheading Architecture Documents
> +
> +For information on the OpenRISC 1000 architecture refer to the
> +@uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}.
> +
> +@section Calling Conventions
> +
> +Please refer to the
> +@uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function
> Calling Sequence}.
> +
> +@subsection Floating Point Unit
> +
> +A floating point unit is currently not supported.
> +
> +@section Memory Model
> +
> +A flat 32-bit memory model is supported.
> +
> +@section Interrupt Processing
> +
> +OpenRISC 1000 architecture has 13 exception types:
> +
> +@itemize @bullet
> +
> +@item Reset
> +@item Bus Error
> +@item Data Page Fault
> +@item Instruction Page Fault
> +@item Tick Timer
> +@item Alignment
> +@item Illegal Instruction
> +@item External Interrupt
> +@item D-TLB Miss
> +@item I-TLB Miss
> +@item Range
> +@item System Call
> +@item Floating Point
> +@item Trap
> +
> +@end itemize
> +
> +@subsection Interrupt Levels
> +
> +There are only two levels: interrupts enabled and interrupts disabled.
> +
> +@subsection Interrupt Stack
> +
> +OpenRISC RTEMS port uses RTEMS SW interrupt stack.
> +The stack for interrupts is allocated during interrupt driver initilization.
> +When an interrup entered, the _ISR_Handler routine is resposible for
> +switching from the interrupted task stack to RTEMS SW interrupt stack.
> +
> +@section Default Fatal Error Processing
> +
> +The default fatal error handler for this architecture performs the
> +following actions:
> +
> +@itemize @bullet
> +@item disables operating system supported interrupts (IRQ),
> +@item places the error code in @code{r0}, and
> +@item executes an infinite loop to simulate a halt processor instruction.
> +@end itemize
> +
> +
--
Joel Sherrill, Ph.D. Director of Research & Development
joel.sherr...@oarcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
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