Hi all, I am trying to optimize the _ISR_Handler code. OpenRISC folks indicated that I can use shadow registers to hold interrupted task context. There are 512 SPRs that can be used for mapping general purpose registers to these SPRs (I guess we can use them for nesting interrupts, given that interrupt level can be an index/base?)
That said, if I mapped task context registers to SPRs, should I populate CPU_Exception_frame from _ISR_Handler? Or I can just use the values from SPRs when needed (i.e, restore interrupted task context before returning from interrupt?) Some functions like print_exception_frame may need the context to be saved in memory. Also, some other C handlers may need a pointer to the frame in memory. Thanks, Hesham _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
