[PATCH] or1k hacks to compile again

[Joel Sherrill]

---
 cpukit/score/cpu/or1k/cpu.c                        |  4 ++-
 cpukit/score/cpu/or1k/or1k-exception-handler-low.S |  1 -
 cpukit/score/cpu/or1k/rtems/score/cpu.h            | 33 +++++++++++++---------
 3 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
index 3be7141..1f02690 100644
--- a/cpukit/score/cpu/or1k/cpu.c
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -153,7 +153,9 @@ void _CPU_Install_interrupt_stack( void )
 {
 }
 
-void _CPU_Context_Initialize_fp (void)
+void _CPU_Context_Initialize_fp(
+  void **fp_context_ptr
+)
 {
 }
 
diff --git a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S 
b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
index d7378cd..ccb1c42 100644
--- a/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
+++ b/cpukit/score/cpu/or1k/or1k-exception-handler-low.S
@@ -21,7 +21,6 @@
 
 #include <rtems/asm.h>
 #include <rtems/score/percpu.h>
-#include <bsp/linker-symbols.h>
 
 .align 4
 .text
diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h 
b/cpukit/score/cpu/or1k/rtems/score/cpu.h
index 4f13852..07f6e5e 100644
--- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
@@ -27,9 +27,9 @@
 extern "C" {
 #endif
 
-#include <stdint.h>
 #include "rtems/score/or1k.h"            /* pick up machine definitions */
 #ifndef ASM
+#include <stdint.h>
 #include "rtems/score/types.h"
 #endif
 
@@ -376,6 +376,7 @@ extern "C" {
  *  
  */
 
+#ifndef ASM
 #ifdef OR1K_64BIT_ARCH
 #define or1kreg uint64_t  
 #else
@@ -644,7 +645,7 @@ typedef enum {
 
 static inline uint32_t or1k_interrupt_disable( void )
 {
-  uint32_t tmp;
+  uint32_t tmp = 0;
   
   __asm__ volatile(           
     "l.mfspr %0,r0,17;"      
@@ -655,12 +656,12 @@ static inline uint32_t or1k_interrupt_disable( void )
     : "memory"  
   ); 
     
-  return 0;
+  return tmp;
 }
 
 static inline void or1k_interrupt_enable(uint32_t level)
 {
-   uint32_t tmp;
+   uint32_t tmp = level;
   
   __asm__ volatile(           
     "l.mfspr %0,r0,17;"      
@@ -670,8 +671,6 @@ static inline void or1k_interrupt_enable(uint32_t level)
     : "r" (tmp) 
     : "memory"
   );
-  
-  return 0;
 }
 
 #define _CPU_ISR_Disable( _isr_cookie ) \
@@ -819,11 +818,10 @@ void _CPU_Context_Initialize(
  *
  */
 
-/*#define _CPU_Context_Initialize_fp( _destination ) \
-  { \
-   *(*(_destination)) = _CPU_Null_fp_context; \
-  }
-*/
+void _CPU_Context_Initialize_fp(
+  void **fp_context_ptr
+);
+
 /* end of Context handler macros */
 
 /* Fatal Error manager macros */
@@ -956,12 +954,17 @@ typedef struct {
 /* There is no CPU specific per-CPU state */
 } CPU_Per_CPU_control;
 
-typedef uint32_t CPU_Counter_ticks;
-typedef uint16_t         Priority_bit_map_Word;
-#define CPU_SIZEOF_POINTER 4
+#endif /* ASM */
 
+#define CPU_SIZEOF_POINTER 4
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+
+#ifndef ASM
+
+typedef uint32_t CPU_Counter_ticks;
+typedef uint16_t Priority_bit_map_Word;
+
 typedef struct {
   uint32_t r[32];
 } CPU_Exception_frame;
@@ -1137,6 +1140,8 @@ typedef uint32_t CPU_Counter_ticks;
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
 
+#endif /* ASM */
+
 #ifdef __cplusplus
 }
 #endif
-- 
1.9.3

_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel