When entering up state, but before enabling interrupts, the icaches are flushed to make sure that changes to the trap table are visible. After up state the SMP cache manager is used to order cache flushes whenever the trap table is altered.
Daniel Cederman (2): bsp/sparc: Flush icache before first time enabling interrupts score/sparc: Flush all cores icache after trap table update c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 9 +++++++++ cpukit/score/cpu/sparc/cpu.c | 23 +++++++++++++++++++++-- cpukit/score/cpu/sparc/rtems/score/cpu.h | 4 ++++ 3 files changed, 34 insertions(+), 2 deletions(-) -- 1.7.9.5 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
