> I guess we could pass an argument to the vectorizer whether to generate > SVE-friendly code. If this is limited to emitting additional TIR builtins, > then I'm ok with that. I just want to be able to reuse as much of the > vectorization code as possible between SVE and non-SVE targets.
@kparzysz-quic I'm somewhat confused about the meaning of "non-SVE targets" there - do you mean targets that don't support VLA programming at all or do you mean other scalable vector architectures like RVV? If it's the latter, then yes, ideally we'd converge to a design that works for all TVM users. > To take full advantage of SVE we'd need to be able to vectorize loops with > iteration count that is not known at compile time, which is the part I'm > interested in. Are you planning to implement that in the near future, or is > this a longer-term goal? Vectorizing a loop with compile time unknown iteration count is core part of this proposal - see the code examples in the RFC. -- Reply to this email directly or view it on GitHub: https://github.com/apache/tvm-rfcs/pull/104#issuecomment-1757817798 You are receiving this because you are subscribed to this thread. Message ID: <apache/tvm-rfcs/pull/104/c1757817...@github.com>
