@MJKlaiber Thanks for the pre-RFC! Overall I'm very supportive of making it 
easier to integrate custom accelerators with TVM. I agree it makes sense to 
consider the set of interfaces an accelerator vendor may need to implement in 
order to bring their accelerator to TVM and try to harmonize them as much as 
possible so that there is a straightforward way to do this. This looks like a 
good way to organize a flow around accelerator development.

One of the challenges with adding several different lowering flows to TVM is 
understanding the advantages and drawbacks of each (hopefully there are really 
not so many drawbacks to any flow, but as with any system I'm sure they exist). 
At a high level, it'd be great if you guys could add additional motivation 
where you depart from the standard flow to explain what is difficult to 
accomplish with the existing standard flow. I definitely want to ensure we have 
flows in TVM to support a wide variety of hardware, but at the same time I want 
to make sure we minimize complexity of the compiler itself. Having this 
additional context will make it easier to understand why we need to override 
the standard flow.

The Prior Art/Alternatives part of the template RFC might also provide some 
framework that would help us to compare this flow with other options.

Couple other questions about the pre-RFC:

[quote="MJKlaiber, post:1, topic:12039"]
The intention is to use TensorIR and Relax with MetaScheduler for optimization.
[/quote]

Just curious where you guys have gotten to with this part of the effort. Will 
this be in the initial PR(s)?

[quote="MJKlaiber, post:1, topic:12039"]
UMACodegen

* Input: NS-TIR(including tir.extern calls)
* ...
* Output: Target .c files
[/quote]

Is it possible to output other things? e.g. if TIR-to-Runtime assembles binary 
programming for an accelerator, is it possible to also output `.bin` or similar?





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