Thank you for your reply!
The example you described is a NDRange Kernel in OpenCL. To better fit the design philosophy of FPGA accelerator, both Xilnix and Intel supported another mode of OpenCL kernel called Single Work-Item Kernel. In fact, both Xilinx and Intel recommends single work-item kernels for FPGA development. https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807516407.html#ewa1397066666833 As a HDL developer, I totally agree with you that the current status of OpenCL is not perfect. A lot of domain-specific design ideas could not be implemented efficiently via OpenCL. On the other hand, manufacturer’s support is crucial for efficient FPGA designs. Many manufacture-/product-/chip-dependent optimizations are hidden and are only available through their respective official synthesizing tools. As both Xilinx and Altera are currently leaning towards OpenCL for HLS, I think we should give it a try to implement our VTA design in OpenCL. --- [Visit Topic](https://discuss.tvm.ai/t/rfc-vta-support-for-cloud-devices-opencl-compatible/6676/10) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.ai/email/unsubscribe/026c934db839d827053140d1d71361eb2c53dc511b05f6ed460789c9c0b442f7).
