For my current use case (RoCC accelerators), yes. Actually I do not even need
a full-scale barrier between the cores: just an `__asm__ volatile("fence");`
would be sufficient. Like I've expressed in the previous reply, I'm wondering
if there can actually be use cases for the `prologue` part, as it was just so
tempting to add that for symmetry with `epilogue`. Otherwise, I do think
something like `barrier` should be better. We might need to look into the
semantics though, as `barrier` has its very meaning to enforce memory
consistency between cores, but `epilogue` can accept arbitrary `void(void)`
functions.
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