There is an active effort (RFC to be released soon by @vegaluis) on providing cycle accurate simulation of the VTA hardware design. For now, we provide software emulation libraries that are open sourced, but don't provide a cycle accurate accounting of what goes on within the chip. The benefit for these software emulation libraries is that they give us very fast emulation (infinite speed simulation as some would call it). This can give you metrics on how many times the tensor core was invoked, how much data was moved from DRAM to SRAM etc. But it won't give us cycle accurate information of what goes on inside of the hardware pipeline.
With the new simulation effort, we'll leverage Verilator to get both decent performance, as well as better visibility into the hardware behavior. Stay tuned for Luis' upcoming RFC. --- [Visit Topic](https://discuss.tvm.ai/t/functional-architecture-performance-simulation-for-vta/1592/3) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.ai/email/unsubscribe/3c73dfffecd9387f390fedfe46d40a4990d79fd234664b1b2db486e74ee77104). Tianqi Chen, UW, Seattle, WA, 98105, United States http://tracking.discuss.tvm.ai/tracking/unsubscribe?msgid=BJsygFUUNXefzivPLQExRw2
