On Fri, Oct 16, 2026 at 3:21 PM <[email protected]> wrote: > > From: Pavan Nikhilesh <[email protected]> > > Use a single predicate for HWWQE enable, fast-path selection and chunk > pool sizing so a TIM_HWWQE_VER_0 device is not run with HWWQE paths > without being configured. Fix the burst response mapping in > cnxk_tim_add_entry_tmo_hwwqe() to match the single timer path. > > With tim_disable_npa, the generic ring ops only align objects to > RTE_MEMPOOL_ALIGN, which does not give the 256B alignment CN20K needs. > Populate the pool from a 256B aligned memzone with the trailer padded > so the object stride is a multiple of 256B, and keep the chunk slot > count within CNXK_TIM_MAX_CHUNK_SLOTS after rounding up. > > Fixes: 19861e9eac8d ("event/cnxk: align CN20K TIM chunk buffers") > > Signed-off-by: Pavan Nikhilesh <[email protected]>
Applied to dpdk-next-eventdev/for-main. Thanks
