These functions were marked for deprecation and no longer used. Drop from EAL.
Signed-off-by: Stephen Hemminger <[email protected]> --- lib/eal/arm/include/rte_atomic_32.h | 6 --- lib/eal/arm/include/rte_atomic_64.h | 6 --- lib/eal/include/generic/rte_atomic.h | 61 -------------------------- lib/eal/loongarch/include/rte_atomic.h | 6 --- lib/eal/ppc/include/rte_atomic.h | 6 --- lib/eal/riscv/include/rte_atomic.h | 6 --- lib/eal/x86/include/rte_atomic.h | 4 -- 7 files changed, 95 deletions(-) diff --git a/lib/eal/arm/include/rte_atomic_32.h b/lib/eal/arm/include/rte_atomic_32.h index 0b9a0dfa30..3809ddefb7 100644 --- a/lib/eal/arm/include/rte_atomic_32.h +++ b/lib/eal/arm/include/rte_atomic_32.h @@ -21,12 +21,6 @@ extern "C" { #define rte_rmb() __sync_synchronize() -#define rte_smp_mb() rte_mb() - -#define rte_smp_wmb() rte_wmb() - -#define rte_smp_rmb() rte_rmb() - #define rte_io_mb() rte_mb() #define rte_io_wmb() rte_wmb() diff --git a/lib/eal/arm/include/rte_atomic_64.h b/lib/eal/arm/include/rte_atomic_64.h index 181bb60929..c9b41f6212 100644 --- a/lib/eal/arm/include/rte_atomic_64.h +++ b/lib/eal/arm/include/rte_atomic_64.h @@ -24,12 +24,6 @@ extern "C" { #define rte_rmb() asm volatile("dmb oshld" : : : "memory") -#define rte_smp_mb() asm volatile("dmb ish" : : : "memory") - -#define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory") - -#define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory") - #define rte_io_mb() rte_mb() #define rte_io_wmb() rte_wmb() diff --git a/lib/eal/include/generic/rte_atomic.h b/lib/eal/include/generic/rte_atomic.h index 0a4f3f8528..937d344c89 100644 --- a/lib/eal/include/generic/rte_atomic.h +++ b/lib/eal/include/generic/rte_atomic.h @@ -51,67 +51,6 @@ static inline void rte_wmb(void); static inline void rte_rmb(void); ///@} -/** @name SMP Memory Barrier - */ -///@{ -/** - * General memory barrier between lcores - * - * Guarantees that the LOAD and STORE operations that precede the - * rte_smp_mb() call are globally visible across the lcores - * before the LOAD and STORE operations that follows it. - * - * @note - * This function is deprecated. - * It provides similar synchronization primitive as atomic fence, - * but has different syntax and memory ordering semantic. Hence - * deprecated for the simplicity of memory ordering semantics in use. - * - * rte_atomic_thread_fence(rte_memory_order_acq_rel) should be used instead. - */ -static inline void rte_smp_mb(void); - -/** - * Write memory barrier between lcores - * - * Guarantees that the STORE operations that precede the - * rte_smp_wmb() call are globally visible across the lcores - * before the STORE operations that follows it. - * - * @note - * This function is deprecated. - * It provides similar synchronization primitive as atomic fence, - * but has different syntax and memory ordering semantic. Hence - * deprecated for the simplicity of memory ordering semantics in use. - * - * rte_atomic_thread_fence(rte_memory_order_release) should be used instead. - * The fence also guarantees LOAD operations that precede the call - * are globally visible across the lcores before the STORE operations - * that follows it. - */ -static inline void rte_smp_wmb(void); - -/** - * Read memory barrier between lcores - * - * Guarantees that the LOAD operations that precede the - * rte_smp_rmb() call are globally visible across the lcores - * before the LOAD operations that follows it. - * - * @note - * This function is deprecated. - * It provides similar synchronization primitive as atomic fence, - * but has different syntax and memory ordering semantic. Hence - * deprecated for the simplicity of memory ordering semantics in use. - * - * rte_atomic_thread_fence(rte_memory_order_acquire) should be used instead. - * The fence also guarantees LOAD operations that precede the call - * are globally visible across the lcores before the STORE operations - * that follows it. - */ -static inline void rte_smp_rmb(void); -///@} - /** @name I/O Memory Barrier */ ///@{ diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h index c8066a4612..49e0c67020 100644 --- a/lib/eal/loongarch/include/rte_atomic.h +++ b/lib/eal/loongarch/include/rte_atomic.h @@ -22,12 +22,6 @@ extern "C" { #define rte_rmb() rte_mb() -#define rte_smp_mb() rte_mb() - -#define rte_smp_wmb() rte_mb() - -#define rte_smp_rmb() rte_mb() - #define rte_io_mb() rte_mb() #define rte_io_wmb() rte_mb() diff --git a/lib/eal/ppc/include/rte_atomic.h b/lib/eal/ppc/include/rte_atomic.h index 10acc238f9..1da5afccbf 100644 --- a/lib/eal/ppc/include/rte_atomic.h +++ b/lib/eal/ppc/include/rte_atomic.h @@ -24,12 +24,6 @@ extern "C" { #define rte_rmb() asm volatile("sync" : : : "memory") -#define rte_smp_mb() rte_mb() - -#define rte_smp_wmb() rte_wmb() - -#define rte_smp_rmb() rte_rmb() - #define rte_io_mb() rte_mb() #define rte_io_wmb() rte_wmb() diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h index 66346ad474..dd10ad5127 100644 --- a/lib/eal/riscv/include/rte_atomic.h +++ b/lib/eal/riscv/include/rte_atomic.h @@ -27,12 +27,6 @@ extern "C" { #define rte_rmb() asm volatile("fence r, r" : : : "memory") -#define rte_smp_mb() rte_mb() - -#define rte_smp_wmb() rte_wmb() - -#define rte_smp_rmb() rte_rmb() - #define rte_io_mb() asm volatile("fence iorw, iorw" : : : "memory") #define rte_io_wmb() asm volatile("fence orw, ow" : : : "memory") diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h index 780fdce871..826b5033d1 100644 --- a/lib/eal/x86/include/rte_atomic.h +++ b/lib/eal/x86/include/rte_atomic.h @@ -23,10 +23,6 @@ #define rte_rmb() _mm_lfence() -#define rte_smp_wmb() rte_compiler_barrier() - -#define rte_smp_rmb() rte_compiler_barrier() - #ifdef __cplusplus extern "C" { #endif -- 2.53.0
