[PATCH v4 1/2] eal/riscv: set default SIMD bitwidth to 128

[Sun Yuechi]

Enable vector code paths on RISC-V platforms with V extension.

Signed-off-by: Sun Yuechi <sunyue...@iscas.ac.cn>
---
 lib/eal/riscv/include/rte_vect.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
index a4357e266a..4d16082449 100644
--- a/lib/eal/riscv/include/rte_vect.h
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -19,7 +19,7 @@
 extern "C" {
 #endif
 
-#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_128
 
 typedef int32_t                xmm_t __attribute__((vector_size(16)));
 
-- 
2.53.0