Update documentation and release notes
update link speed capabilities for 200G and 400G
Signed-off-by: Ed Czeck <ed.cz...@atomicrules.com>
---
v2:
- included 2 more device id
- updated link speeds
---
doc/guides/nics/ark.rst | 7 +++++++
drivers/net/ark/ark_ethdev.c | 10 +++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/ark.rst b/doc/guides/nics/ark.rst
index 6aabde2ed5..c8ed57289b 100644
--- a/doc/guides/nics/ark.rst
+++ b/doc/guides/nics/ark.rst
@@ -310,6 +310,12 @@ ARK PMD supports the following Arkville RTL PCIe instances
including:
* ``1d6c:1024`` - AR-TK242 [2x100GbE Packet Capture Device]
* ``1d6c:1025`` - AR-TK242-FX2 [2x100GbE Gen5 Packet Capture Device]
* ``1d6c:1026`` - AR-TK242-FX2 [1x200GbE Gen5 Packet Capture Device]
+* ``1d6c:102a`` - AR-TK242-FX2 [4x100GbE Gen5 Packet Capture Device]
+* ``1d6c:102b`` - AR-ARKV-FX1 [Arkville 128B DPDK Data Mover for Versal/CPM5]
+* ``1d6c:102c`` - AR-TK242-V80 [Gen5 PCAP Processor]
+* ``1d6c:102d`` - AR-TK242-FX2 [8x10GbE Gen5 Packet Capture-Replay Device]
+* ``1d6c:102e`` - AR-TK242-FX2 [8x25GbE Gen5 Packet Capture-Replay Device]
+* ``1d6c:102f`` - AR-TK242-FX2 [1x400GbE Gen5 Packet Capture-Replay Device]
Arkville RTL Core Configurations
--------------------------------
@@ -322,6 +328,7 @@ stream interfaces for both AMD/Xilinx and Intel FPGAs.
* ARK-FX0 - 256-bit 32B datapath (PCIe Gen3, Gen4)
* ARK-FX1 - 512-bit 64B datapath (PCIe Gen3, Gen4, Gen5)
+* ARKV-FX1 - 1024-bit 128B datapath (AMD PCIe Versal, Gen5 )
* ARK-FX2 - 1024-bit 128B datapath (PCIe Gen5x16 Only)
DPDK and Arkville Firmware Versioning
diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c
index c029dc46b3..8d3c0a1b02 100644
--- a/drivers/net/ark/ark_ethdev.c
+++ b/drivers/net/ark/ark_ethdev.c
@@ -102,6 +102,12 @@ static const struct rte_pci_id pci_id_ark_map[] = {
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1024)},
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1025)},
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1026)},
+ {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x102a)},
+ {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x102b)},
+ {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x102c)},
+ {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x102d)},
+ {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x102e)},
+ {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x102f)},
{.vendor_id = 0, /* sentinel */ },
};
@@ -733,7 +739,9 @@ eth_ark_dev_info_get(struct rte_eth_dev *dev,
RTE_ETH_LINK_SPEED_25G |
RTE_ETH_LINK_SPEED_40G |
RTE_ETH_LINK_SPEED_50G |
- RTE_ETH_LINK_SPEED_100G);
+ RTE_ETH_LINK_SPEED_100G |
+ RTE_ETH_LINK_SPEED_200G |
+ RTE_ETH_LINK_SPEED_400G);
dev_info->rx_offload_capa = RTE_ETH_RX_OFFLOAD_TIMESTAMP;
--
2.34.1
