NVIDIA NICs do not support matching on packet headers appearing
after IP header if the received packet is an IP fragment.
This patch updates the relevant documentation.

Bugzilla ID: 1417

Signed-off-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
---
Depends-on: series-35735 ("rework mlx5 guide")

FYI - I added Bugzilla ticket ID just for reference.
Patch does not resolve the issue, just adds missing documentation
for existing limitation.

 doc/guides/nics/mlx5.rst | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index f29408eace..f58fea106a 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -3305,6 +3305,13 @@ Limitations

 #. IP-in-IP is not supported with :ref:`HW steering <mlx5_hws>`.

+#. Matching on packet headers appearing after an IP header is not supported
+   if that packet is an IP fragment:
+
+   - For example: If a flow rule with pattern matching on L4 header contents 
is created,
+     and the first IP fragment is received,
+     then this IP fragment will miss on that flow rule.
+

 .. _mlx5_nat64:

--
2.39.5

Reply via email to