The txq_calc_wqebb_cnt() should be aligned with the calculation in
the function mlx5_txq_devx_obj_new(). Or when the input descriptor
number is 512, the WQE size will be wrongly considered to be 30 when
no max_inline_data is set. The total number of WQE will be considered
as 256 and that is incorrect.
Fixes: 38b4b397a57d ("net/mlx5: add Tx configuration and setup")
Cc: viachesl...@mellanox.com
Signed-off-by: Bing Zhao <bi...@nvidia.com>
---
drivers/net/mlx5/mlx5_txq.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 5fee5bc4e8..2fdb472ab3 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -706,9 +706,15 @@ txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
wqe_size = MLX5_WQE_CSEG_SIZE +
MLX5_WQE_ESEG_SIZE +
- MLX5_WSEG_SIZE -
- MLX5_ESEG_MIN_INLINE_SIZE +
- txq_ctrl->max_inline_data;
+ MLX5_WSEG_SIZE;
+ wqe_size += txq_ctrl->txq.tso_en ?
+ RTE_ALIGN(txq_ctrl->max_tso_header, MLX5_WSEG_SIZE) : 0;
+ if (txq_ctrl->txq.inlen_send)
+ wqe_size = RTE_MAX(wqe_size, MLX5_WQE_CSEG_SIZE +
+ MLX5_WQE_ESEG_SIZE +
+ RTE_ALIGN(txq_ctrl->txq.inlen_send
+
+ sizeof(uint32_t),
+ MLX5_WSEG_SIZE));
return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
}
--
2.34.1
