From: Igor Romanov <igor.roma...@oktetlabs.ru>
Size of Tx descriptor is different on Riverhead. So, the size
should be a part of NIC config, not a macro that is common for
all NIC families.
Signed-off-by: Igor Romanov <igor.roma...@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybche...@solarflare.com>
---
drivers/net/sfc/base/ef10_impl.h | 2 ++
drivers/net/sfc/base/ef10_tx.c | 7 ++++---
drivers/net/sfc/base/efx.h | 21 +++++++++++++++++++++
drivers/net/sfc/base/efx_tx.c | 18 ++++++++++++++++++
drivers/net/sfc/base/hunt_nic.c | 2 ++
drivers/net/sfc/base/medford2_nic.c | 2 ++
drivers/net/sfc/base/medford_nic.c | 2 ++
drivers/net/sfc/base/siena_impl.h | 2 ++
drivers/net/sfc/base/siena_nic.c | 2 ++
9 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h
index 12747f43c..0116bc91c 100644
--- a/drivers/net/sfc/base/ef10_impl.h
+++ b/drivers/net/sfc/base/ef10_impl.h
@@ -19,6 +19,8 @@ extern "C" {
#define EF10_TXQ_MINNDESCS 512
+#define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
+
/* Maximum independent of EFX_BUG35388_WORKAROUND. */
#define EF10_TXQ_MAXNBUFS 8
diff --git a/drivers/net/sfc/base/ef10_tx.c b/drivers/net/sfc/base/ef10_tx.c
index aacf4310a..82be77f13 100644
--- a/drivers/net/sfc/base/ef10_tx.c
+++ b/drivers/net/sfc/base/ef10_tx.c
@@ -41,14 +41,15 @@ efx_mcdi_init_txq(
efx_rc_t rc;
EFSYS_ASSERT(EF10_TXQ_MAXNBUFS >=
- EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
+ efx_txq_nbufs(enp, enp->en_nic_cfg.enc_txq_max_ndescs));
- if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_TXQ_SIZE(ndescs))) {
+ if ((esmp == NULL) ||
+ (EFSYS_MEM_SIZE(esmp) < efx_txq_size(enp, ndescs))) {
rc = EINVAL;
goto fail1;
}
- npages = EFX_TXQ_NBUFS(ndescs);
+ npages = efx_txq_nbufs(enp, ndescs);
if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
rc = EINVAL;
goto fail2;
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 8aa03b538..506bdb5e1 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1284,6 +1284,7 @@ typedef struct efx_nic_cfg_s {
uint32_t enc_evq_timer_quantum_ns;
uint32_t enc_evq_timer_max_us;
uint32_t enc_clk_mult;
+ uint32_t enc_tx_desc_size;
uint32_t enc_rx_prefix_size;
uint32_t enc_rx_buf_align_start;
uint32_t enc_rx_buf_align_end;
@@ -2645,8 +2646,28 @@ efx_tx_fini(
*/
#define EFX_TXQ_MINNDESCS 512
+/*
+ * This macro is deprecated and will be removed.
+ * Use the function efx_txq_size() instead.
+ */
#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof
(efx_qword_t))
+
+/*
+ * This macro is deprecated and will be removed.
+ * Use the function efx_txq_nbufs() instead.
+ */
#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) /
EFX_BUF_SIZE)
+
+extern __checkReturn size_t
+efx_txq_size(
+ __in const efx_nic_t *enp,
+ __in unsigned int ndescs);
+
+extern __checkReturn unsigned int
+efx_txq_nbufs(
+ __in const efx_nic_t *enp,
+ __in unsigned int ndescs);
+
#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
#define EFX_TXQ_CKSUM_IPV4 0x0001
diff --git a/drivers/net/sfc/base/efx_tx.c b/drivers/net/sfc/base/efx_tx.c
index b777a85c5..bbe2bd1b7 100644
--- a/drivers/net/sfc/base/efx_tx.c
+++ b/drivers/net/sfc/base/efx_tx.c
@@ -297,6 +297,24 @@ efx_tx_fini(
enp->en_mod_flags &= ~EFX_MOD_TX;
}
+ __checkReturn size_t
+efx_txq_size(
+ __in const efx_nic_t *enp,
+ __in unsigned int ndescs)
+{
+ const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
+
+ return (ndescs * encp->enc_tx_desc_size);
+}
+
+ __checkReturn unsigned int
+efx_txq_nbufs(
+ __in const efx_nic_t *enp,
+ __in unsigned int ndescs)
+{
+ return (efx_txq_size(enp, ndescs) / EFX_BUF_SIZE);
+}
+
__checkReturn efx_rc_t
efx_tx_qcreate(
__in efx_nic_t *enp,
diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 755a377f0..b4fc3cc9e 100644
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -186,6 +186,8 @@ hunt_board_cfg(
/* Checksums for TSO sends can be incorrect on Huntington. */
encp->enc_bug61297_workaround = B_TRUE;
+ encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
diff --git a/drivers/net/sfc/base/medford2_nic.c
b/drivers/net/sfc/base/medford2_nic.c
index 3274744d9..9cfc5077c 100644
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -101,6 +101,8 @@ medford2_board_cfg(
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
+ encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
diff --git a/drivers/net/sfc/base/medford_nic.c
b/drivers/net/sfc/base/medford_nic.c
index cb107fe75..3f2c5b877 100644
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -99,6 +99,8 @@ medford_board_cfg(
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
+ encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
diff --git a/drivers/net/sfc/base/siena_impl.h
b/drivers/net/sfc/base/siena_impl.h
index caab29af0..6f07b1ec7 100644
--- a/drivers/net/sfc/base/siena_impl.h
+++ b/drivers/net/sfc/base/siena_impl.h
@@ -34,6 +34,8 @@ extern "C" {
#define SIENA_RXQ_MAXNDESCS 4096
#define SIENA_RXQ_MINNDESCS 512
+#define SIENA_TXQ_DESC_SIZE (sizeof (efx_qword_t))
+
#define SIENA_NVRAM_CHUNK 0x80
diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c
index 4962a65c5..987a32d2f 100644
--- a/drivers/net/sfc/base/siena_nic.c
+++ b/drivers/net/sfc/base/siena_nic.c
@@ -104,6 +104,8 @@ siena_board_cfg(
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
+ encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
+
/* When hash header insertion is enabled, Siena inserts 16 bytes */
encp->enc_rx_prefix_size = 16;
--
2.17.1
