Timo Aaltonen pushed to branch debian-experimental at X Strike Force / lib / mesa
Commits: f510e6a1 by Dylan Baker at 2025-10-16T11:37:29-07:00 .pick_status.json: Update to 3b2f7ed918a5ad78c1d3756e9823a1616c1f21d7 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 9bb7bf9c by Lionel Landwerlin at 2025-10-16T11:37:36-07:00 Revert "wsi: Implements scaling controls for DRI3 presentation." This reverts commit a219308867e7cee0f3bef3f0ebc14d99c665882f. It's failing most of the tests on Anv : $ ./deqp-vk -n dEQP-VK.wsi.xlib.maintenance1.scaling.* Test run totals: Passed: 88/2422 (3.6%) Failed: 576/2422 (23.8%) Not supported: 1758/2422 (72.6%) Warnings: 0/2422 (0.0%) Waived: 0/2422 (0.0%) The only passing tests seem to be with this pattern : dEQP-VK.wsi.xlib.maintenance1.scaling.*.same_size_and_aspect (cherry picked from commit 2baa3b8c06ab067ae78d4a924856d2d811975fec) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - fd6b9c70 by Valentine Burley at 2025-10-16T11:37:37-07:00 docs: Update LAVA caching setup After a recent change, `piglit-traces.sh` automatically sets the caching proxy, so update the docs to reflect this. Also update the name of the variable from `FDO_HTTP_CACHE_URI` to `LAVA_HTTP_CACHE_URI`. Fixes: fa74e939bfd ("ci/piglit: automatically use LAVA proxy") Signed-off-by: Valentine Burley <[email protected]> (cherry picked from commit 28e73a62399f5010d4c4d67f2cae2e313c05dbfb) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 84655b4b by Lionel Landwerlin at 2025-10-16T11:37:38-07:00 anv: fix image-to-image copies of TileW images The intermediate buffer between the 2 images is linear, its stride should be a function of the tile's logical width. Normally this should map to the values reported by ISL except for TileW where for some reason it was decided to report 128 for TileW instead of the actual 64 size (see isl_tiling_get_info() ISL_TILING_W case) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: mesa-stable Reviewed-by: Alyssa Rosenzweig <[email protected]> (cherry picked from commit 77fb8fb062457dad73bd763e97bf757b6cd04080) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 289c768e by Dylan Baker at 2025-10-17T07:40:05-07:00 .pick_status.json: Update to ad421cdf2e68a1ccef80cb810c012c8469579cb6 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 87113943 by Dylan Baker at 2025-10-17T07:41:23-07:00 .pick_status.json: Mark c20e2733bf8f9bb595f1bcc68ebb3d0686ef28e4 as denominated Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 45aafef6 by Xaver Hugl at 2025-10-17T07:41:25-07:00 vulkan/wsi: require extended target volume support for scRGB It's hardly going to be useful without that Signed-off-by: Xaver Hugl <[email protected]> Fixes: 4b663d56 ("vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland") (cherry picked from commit 892cf427a0f62538a6943fd7500a9b23f0dd91ea) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - ca7d2daf by Marek Olšák at 2025-10-17T07:41:27-07:00 r300: fix DXTC blits Fixes: 9d359c6d10ad - gallium: delete pipe_surface::width and pipe_surface::height (cherry picked from commit 733ba77bfe7fc200257eae6eac098b6577c705e3) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 756618ee by Mike Blumenkrantz at 2025-10-17T07:41:28-07:00 zink: consistently set/unset msrtss in begin_rendering this has to always be set or unset, never persistent from previous renderpass Fixes: 5080f2b6f55 ("zink: disable msrtss handling when blitting") (cherry picked from commit f74cf450782509d9e386a83a3f8221a3d1bdb701) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 674e2a70 by Josh Simmons at 2025-10-17T07:41:29-07:00 radv: Fix crash in sqtt due to uninitalized value Fixes: 772b9ce4118 ("radv: Remove qf from radv_spm/sqtt/perfcounter where applicable") Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit b10c1a195266b0df668b3b5490223f648075bed1) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 42ab1c6f by Job Noorman at 2025-10-17T07:41:30-07:00 nir: mark fneg distribution through fadd/ffma as nsz df1876f615a ("nir: Mark negative re-distribution on fadd as imprecise") fixed the fadd case by marking it as imprecise. This commit fixes the ffma case for the same reason. However, "imprecise" isn't necessary and nowadays we have "nsz" which is more accurate here. Use that for both fadd and ffma. Signed-off-by: Job Noorman <[email protected]> Fixes: 62795475e8f ("nir/algebraic: Distribute source modifiers into instructions") Reviewed-by: Georg Lehmann <[email protected]> (cherry picked from commit ad421cdf2e68a1ccef80cb810c012c8469579cb6) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 30ba8880 by Dylan Baker at 2025-10-21T14:42:24-07:00 .pick_status.json: Update to 28fbc6addbda2ce3e264b41b6ad91a7a0d8eb788 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - c3cf272a by Benjamin Cheng at 2025-10-21T14:42:25-07:00 radv/video: Fill maxCodedExtent caps first Later code (i.e. max qp map extent filling) depends on this. Fixes: ae6ea69c851 ("radv: Implement VK_KHR_video_encode_quantization_map") Reviewed-by: David Rosca <[email protected]> (cherry picked from commit b1370e1935cf958b440b67b9f471499af8bc8ac8) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - bf9e1f2e by Marek Olšák at 2025-10-21T14:42:26-07:00 winsys/radeon: fix completely broken tessellation for gfx6-7 The info was moved to radeon_info, but it was only set for the amdgpu kernel driver. It was uninitialized for radeon. Fixes: d82eda72a1fe3932 - ac/gpu_info: move HS info into radeon_info Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> (cherry picked from commit f5b648f6d30697363d3326f408a50ae87587b1bc) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 40ff53c5 by Emma Anholt at 2025-10-21T14:42:27-07:00 wsi: Fix the flagging of dma_buf_sync_file for the amdgpu workaround. In my regression fix, I covered one of the two paths that had stopped setting the implicit_sync flag and thus triggered the amdgpu behavior we don't want, but probably the less common one. Fixes: f7cbc7b1c56c ("radv: Allocate BOs as implicit sync even if the WSI is doing implicit sync.") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13942 (cherry picked from commit aa96444149fd92f80467f215985b4c39f4c00fd5) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 717e8a8c by Jose Maria Casanova Crespo at 2025-10-21T14:42:27-07:00 v3d: mark FRAG_RESULT_COLOR as output_written on SAND blits FS With the introduction of "v3d: Add support for 16bit normalised formats" https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35820 nir_lower_fragcolor is always called if shaders outputs_written shows that FRAG_RESULT_COLOR is used. But on SAND8/30 blit fragment shaders although the FRAG_RESULT_COLOR is used, it was not marked as output_written so the lowering was not applied. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14141 Fixes: ee48e81b26e ("v3d: Always lower frag color") Reviewed-by: Iago Toral Quiroga <[email protected]> (cherry picked from commit a131530dd14b3def7c67496c2b62ccc04c70d49e) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 602b4a29 by Patrick Lerda at 2025-10-21T14:42:28-07:00 r600: fix r600_draw_rectangle refcnt imbalance The object buf is referenced at the beginning of the r600_draw_rectangle() function and should be freed at the end. This issue was introduced with cbb6e0277f68. Fixes: cbb6e0277f68 ("r600: stop using util_set_vertex_buffers") Signed-off-by: Patrick Lerda <[email protected]> (cherry picked from commit 3b1e3a40a80bd874bc97d13846c0380313c6e7e8) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 14544ef2 by Patrick Lerda at 2025-10-21T14:42:28-07:00 r600: update nplanes support This change fixes "piglit/bin/ext_image_dma_buf_import-export -auto". Fixes: 02aaf360ae38 ("r600: Implement resource_get_param") Signed-off-by: Patrick Lerda <[email protected]> (cherry picked from commit 84dc9af3d4c1a2adc6b62e3773b0ccd6dbacf77b) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 13fa1460 by Timur Kristóf at 2025-10-21T14:42:29-07:00 ac/nir/ngg_mesh: Lower num_subgroups to constant Mesh shader workgroups always have the same amount of subgroups. When the API workgroup size is the same as the real workgroup size, this is a small optimization (using a constant instead of a shader arg). When the API workgroup size is smaller than the real workgroup size (eg. when the number of output vertices or primitves is greater than the API workgroup size on RDNA 2), this fixes a potential bug because num_subgroups would return the "real" workgroup size instead of the API one. Cc: mesa-stable Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Qiang Yu <[email protected]> (cherry picked from commit d20049b430b60e1ece5bef504a3b3f694a83aa1c) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - a02d8d57 by Yiwei Zhang at 2025-10-21T14:42:29-07:00 panvk: fix to advance vs driver_set properly Should only set once outside the multidraw loop so that per draw can patch its own own desc attribs when needed. Fixes: a5a0dd3ccc0 ("panvk: Implement multiDrawIndirect for v10+") Reviewed-by: Boris Brezillon <[email protected]> Acked-by: Christoph Pillmayer <[email protected]> (cherry picked from commit 800c4d34306efb1e67734cefb1e75bf2b8ef2013) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - ab7bda0a by Yiwei Zhang at 2025-10-21T14:42:29-07:00 panvk: fix to advance vs res_table properly Fix a regression from an unfortunate typo. Fixes: 48e8d6d207a ("panfrost, panvk: The size of resource tables needs to be a multiple of 4.") Reviewed-by: Boris Brezillon <[email protected]> Reviewed-by: Christoph Pillmayer <[email protected]> (cherry picked from commit 387f75f43ddbc036c2070e8386deb180282f420a) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 5dcc6564 by Emma Anholt at 2025-10-21T14:42:47-07:00 nir/shrink_stores: Don't shrink stores to an invalid num_components. Avoids a regression in the CL CTS on the next commit. Fixes: 2dba7e60567f ("nir: split nir_opt_shrink_stores from nir_opt_shrink_vectors") (cherry picked from commit 537cc4e0ffc1b8c3f1b6a9857749102723775a78) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 847ad886 by Mel Henning at 2025-10-21T14:42:48-07:00 nvk: Really fix maxVariableDescriptorCount w/ iub I didn't test "nvk: Fix maxVariableDescriptorCount with iub" as thoroughly as I should have and it regressed dEQP-VK.api.maintenance3_check.descriptor_set because we were then violating the requirement that maxPerSetDescriptors describes a limit that's guaranteed to be supported (and reported as supported in GetDescriptorSetLayoutSupport). That commit was also based on a misreading of nvk_nir_lower_descriptors.c where I thought that the end offset of an inline uniform block needed to be less than the size of a UBO. That is not the case - on closer inspection that code gracefully falls back to placing IUBs in globablmem if necessary. So, we can afford to be less strict about our IUB sizing and only require that IUBs follow the existing limit imposed by maxInlineUniformBlockSize. Fixes: ff7f785f09ce ("nvk: Fix maxVariableDescriptorCount with iub") Reviewed-by: Faith Ekstrand <[email protected]> (cherry picked from commit 77cd629b34f67b7035ae9c167ce1fedefe75ce32) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - f656d062 by Lionel Landwerlin at 2025-10-21T14:42:50-07:00 brw: constant fold u2u16 conversion on MCS messages Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: bddfbe7fb1 ("brw/blorp: lower MCS fetching in NIR") Reviewed-by: Alyssa Rosenzweig <[email protected]> (cherry picked from commit f48c9c3a3730c6beef311c2f33d06190b08de1c9) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 0d100cc0 by Lionel Landwerlin at 2025-10-21T14:42:50-07:00 brw: only consider cross lane access on non scalar VGRFs Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 1bff4f93ca ("brw: Basic infrastructure to store convergent values as scalars") Reviewed-by: Francisco Jerez <[email protected]> (cherry picked from commit 70aa028f274f5c25a4d38ba64f327557dbbb0c9e) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - dbbadebe by Lionel Landwerlin at 2025-10-21T14:42:51-07:00 brw: fix ballot() type operations in shaders with HALT instructions Fixes dEQP-VK.reconvergence.terminate_invocation.bit_count LNL fossildb stats: Totals from 16489 (3.36% of 490184) affected shaders: Instrs: 3710499 -> 3710500 (+0.00%) Cycle count: 91601018 -> 90305642 (-1.41%); split: -1.81%, +0.40% Max dispatch width: 523936 -> 523952 (+0.00%); split: +0.02%, -0.01% Signed-off-by: Lionel Landwerlin <[email protected]> Cc: mesa-stable Reviewed-by: Francisco Jerez <[email protected]> (cherry picked from commit 757c042e39a3281999cd65ede1ad508159ae15d4) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - e982234b by Lionel Landwerlin at 2025-10-21T14:42:52-07:00 nir/divergence: fix handling of intel uniform block load Those are normally uniform always, but for the purpose of fused threads handling, we need to check their sources. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: ca1533cd03 ("nir/divergence: add a new mode to cover fused threads on Intel HW") Reviewed-by: Alyssa Rosenzweig <[email protected]> (cherry picked from commit 255d1e883d76d80e2ad5a796814ca0a9483c2ca6) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 1941ada4 by Faith Ekstrand at 2025-10-21T14:42:52-07:00 panvk: Fix integer dot product properties We already set has_[su]dot_4x8[_sat] in nir_shader_compiler_options so we're already getting the opcodes. We just need to advertise the features properly. If bifrost_compile.h is to be believed, those are all available starting at gen 9. Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/218 Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/219 Fixes: f7f9b3d170f5 ("panvk: Move to vk_properties") Reviewed-by: Mary Guillemard <[email protected]> Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]> (cherry picked from commit 38950083ae9fe5650150614687c7c46342d71d02) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 7b7cb63a by Karol Herbst at 2025-10-21T14:42:53-07:00 nak: extract cmat load/store element offset calculation Reviewed-by: Faith Ekstrand <[email protected]> Fixes: 05dca161437 ("nak: extract nir_intrinsic_cmat_load lowering into a function") (cherry picked from commit f632bfc71559b6f60d9f1f4657d21b66a102bc6a) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 425c49eb by Karol Herbst at 2025-10-21T14:42:54-07:00 nak: ensure deref has a ptr_stride in cmat load/store lowering With untyped pointer we might get a deref_cast with a 0 ptr_stride. But we were supposed to ignore the stride information on the pointer anyway, so let's do that properly now. Reviewed-by: Faith Ekstrand <[email protected]> Fixes: 05dca161437 ("nak: extract nir_intrinsic_cmat_load lowering into a function") (cherry picked from commit 3bbf3f782674a25bbca01ca8dee8f58a2c33300c) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 9c57c0a1 by Karol Herbst at 2025-10-21T14:42:54-07:00 nak: fix MMA latencies on Ampere Acked-by: Faith Ekstrand <[email protected]> Fixes: 7a01953a396 ("nak: Add Ampere and Ada latency information") (cherry picked from commit e7dca5a6ca3ab4f2215d48292bfa3bbb3aab6d2c) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 7a30a71c by Mel Henning at 2025-10-21T14:42:55-07:00 nvk: VK_DEPENDENCY_ASYMMETRIC_EVENT_BIT_KHR This was missed in the original maintenance9 MR. Fixes the flakes in test dEQP-VK.synchronization2.op.single_queue.event.write_ssbo_compute_read_ssbo_compute.buffer_16384_maintenance9 Fixes: 7692d3c0 ("nvk: Advertise VK_KHR_maintenance9") Reviewed-by: Faith Ekstrand <[email protected]> (cherry picked from commit 28fbc6addbda2ce3e264b41b6ad91a7a0d8eb788) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 2a8f2ff3 by Dylan Baker at 2025-10-22T09:03:27-07:00 .pick_status.json: Update to e38491eb1850ab8b0082716b00f514f75e2a0e1a Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - e967da84 by Rhys Perry at 2025-10-22T09:03:31-07:00 amd/lower_mem_access_bit_sizes: don't create subdword UBO loads with LLVM These are unsupported. Signed-off-by: Rhys Perry <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14127 Fixes: fbf0399517ae ("amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes") Reviewed-by: Georg Lehmann <[email protected]> (cherry picked from commit 79b2fa785d51d21e56d3647ee5abb6cb78edab7a) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 2b8675fd by Rhys Perry at 2025-10-22T09:03:32-07:00 amd/lower_mem_access_bit_sizes: improve subdword/unaligned SMEM lowering Summary of changes: - handle unaligned 16-bit scalar loads when supported_dword=true - increases the size of 8/16/32/64-bit buffer loads which are not dword aligned, which can create less SMEM loads. - handles when "bytes" is less than "bit_size / 8" fossil-db (gfx1201): Totals from 26 (0.03% of 79839) affected shaders: Instrs: 12676 -> 12710 (+0.27%); split: -0.30%, +0.57% CodeSize: 67272 -> 67384 (+0.17%); split: -0.24%, +0.40% Latency: 44399 -> 44375 (-0.05%); split: -0.09%, +0.04% SClause: 352 -> 344 (-2.27%) SALU: 3972 -> 3992 (+0.50%) SMEM: 554 -> 528 (-4.69%) fossil-db (navi21): Totals from 6 (0.01% of 79825) affected shaders: Instrs: 2192 -> 2186 (-0.27%) CodeSize: 12188 -> 12140 (-0.39%) Latency: 10037 -> 10033 (-0.04%); split: -0.12%, +0.08% SMEM: 124 -> 118 (-4.84%) Signed-off-by: Rhys Perry <[email protected]> Fixes: fbf0399517ae ("amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes") Reviewed-by: Georg Lehmann <[email protected]> (cherry picked from commit 8829fc3bd64b9f2ac62f2339fa9cf6fc0a149cba) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - c1cf6e75 by Rhys Perry at 2025-10-22T09:03:34-07:00 amd/lower_mem_access_bit_sizes: be more careful with 8/16-bit scratch load Signed-off-by: Rhys Perry <[email protected]> Backport-to: 25.3 Reviewed-by: Georg Lehmann <[email protected]> (cherry picked from commit e89b22280fe5f65dfdd749af0f5da892d0bb9dda) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 10475e8a by Rhys Perry at 2025-10-22T09:03:36-07:00 amd/lower_mem_access_bit_sizes: fix shared access when bytes<bit_size/8 This can happen with (for example) 32x2 loads with align_mul=4,align_offset=2. This patch does bit_size=min(bit_size,bytes) to prevent num_components from being 0. Signed-off-by: Rhys Perry <[email protected]> Fixes: 52cd5f7e69fd ("ac/nir_lower_mem_access_bit_sizes: Split unsupported shared memory instructions") Reviewed-by: Georg Lehmann <[email protected]> (cherry picked from commit b18421ae3d20645aea615ff4b2ae2e6c544a7b1f) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 4202ea6c by Olivia Lee at 2025-10-22T09:03:37-07:00 panfrost: fix cl_local_size for precompiled shaders nir_lower_compute_system_values will attempt to lower load_workgroup_size unless workgroup_size_variable is set. For precomp shaders, the workgroup size is set statically for each entrypoint by nir_precompiled_build_variant. Because we call lower_compute_system_values early, it sets the workgroup size to zero. Temporarily setting workgroup_size_variable while we are still processing all the entrypoints together inhibits this. Signed-off-by: Olivia Lee <[email protected]> Fixes: 20970bcd965 ("panfrost: Add base of OpenCL C infrastructure") Reviewed-by: Eric R. Smith <[email protected]> Reviewed-by: Mary Guillemard <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]> (cherry picked from commit a410d90fd254dd4930e72547de430a8cf5daf13b) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 94ec7c68 by Faith Ekstrand at 2025-10-22T09:03:37-07:00 util: Don't advertise cache ops on x86 without SSE2 Fixes: 555881e57499 ("util/cache_ops: Add some cache flush helpers") Reviewed-by: Mel Henning <[email protected]> (cherry picked from commit 3739d7a90c3d2406a3297a973c3de4c3dbe83050) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 0182cde8 by Faith Ekstrand at 2025-10-22T09:03:38-07:00 util: Build util/cache_ops_x86.c with -msse2 __builtin_ia32_clflush() requires -msse2 so we need to set -msse2 at least for building that file. Fortunately, there are no GPUs that actually need userspace cache flushing that can ever be bolted onto a pre-SSE2 x86 CPUs. Fixes: 555881e57499 ("util/cache_ops: Add some cache flush helpers") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14134 Reviewed-by: Mel Henning <[email protected]> (cherry picked from commit efbecd93baa35b4bbeb5f370893865568a577e6e) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - 49bfddbd by Pierre-Eric Pelloux-Prayer at 2025-10-22T09:03:39-07:00 radeonsi: propagate shader updates for merged shaders In case of merged shaders (eg: VS+GS), a change to VS should trigger a GS update. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13935 Fixes: b1a34ac95df ("radeonsi: change do_update_shaders boolean to a bitmask") Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 90103fe61862b8cd3703dea5d906244f1bc61e4f) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - be191cef by Benjamin Cheng at 2025-10-22T09:03:39-07:00 radv/video_enc: Cleanup slice count assert This was left over when first enabling multiple slice encoding. Fixes: 63e952ff2cc ("radv/video: Support encoding multiple slices") Reviewed-by: David Rosca <[email protected]> (cherry picked from commit b6d6c1af73b1e1cad5f84b59eaedad4faacd8dda) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010> - - - - - d9812eae by Dylan Baker at 2025-10-22T16:13:33-07:00 VERSION: bump for rc2 Signed-off-by: Dylan Baker <[email protected]> - - - - - 0e63395c by Timo Aaltonen at 2025-10-24T09:53:27+03:00 Merge branch 'upstream-experimental' into debian-experimental - - - - - b599579c by Timo Aaltonen at 2025-10-24T09:54:16+03:00 version bump - - - - - 0b61a005 by Timo Aaltonen at 2025-10-24T13:49:05+03:00 rules: Add rocket gallium driver for arm. (Closes: #1118656) - - - - - 1a396af4 by Timo Aaltonen at 2025-10-24T21:38:15+03:00 releasing package mesa version 25.3.0~rc2-1 - - - - - 1554190e by Timo Aaltonen at 2025-10-26T11:35:06+02:00 rules: Enable anti-lag and screenshot vulkan layers. - - - - - 7bb38c36 by Timo Aaltonen at 2025-10-27T09:20:22+02:00 control: Limit rocket to arm64. - - - - - 41 changed files: - + .pick_status.json - VERSION - debian/changelog - debian/rules - docs/ci/LAVA.rst - src/amd/common/nir/ac_nir_lower_mem_access_bit_sizes.c - src/amd/common/nir/ac_nir_lower_ngg_mesh.c - src/amd/vulkan/radv_sqtt.c - src/amd/vulkan/radv_video.c - src/amd/vulkan/radv_video_enc.c - src/compiler/nir/nir_divergence_analysis.c - src/compiler/nir/nir_opt_algebraic.py - src/compiler/nir/nir_opt_shrink_stores.c - src/compiler/nir/nir_precompiled.h - src/gallium/drivers/r300/ci/r300-rs740-fails.txt - src/gallium/drivers/r300/ci/r300-rv410-fails.txt - src/gallium/drivers/r300/ci/r300-rv530-nohiz-fails.txt - src/gallium/drivers/r300/r300_state.c - src/gallium/drivers/r600/r600_pipe_common.c - src/gallium/drivers/r600/r600_texture.c - src/gallium/drivers/radeonsi/si_state_draw.cpp - src/gallium/drivers/v3d/v3d_blit.c - src/gallium/drivers/zink/zink_context.c - src/gallium/winsys/radeon/drm/meson.build - src/gallium/winsys/radeon/drm/radeon_drm_winsys.c - src/intel/compiler/brw/brw_nir.c - src/intel/compiler/brw/brw_schedule_instructions.cpp - src/intel/vulkan/anv_image_host_copy.c - src/nouveau/compiler/nak/sm80_instr_latencies.rs - src/nouveau/compiler/nak_nir_lower_cmat.c - src/nouveau/vulkan/nvk_cmd_buffer.c - src/nouveau/vulkan/nvk_descriptor_set_layout.c - src/panfrost/clc/pan_compile.c - src/panfrost/vulkan/csf/panvk_vX_cmd_draw.c - src/panfrost/vulkan/panvk_vX_physical_device.c - src/util/cache_ops.h - src/util/meson.build - src/vulkan/wsi/wsi_common_drm.c - src/vulkan/wsi/wsi_common_private.h - src/vulkan/wsi/wsi_common_wayland.c - src/vulkan/wsi/wsi_common_x11.c The diff was not included because it is too large. View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/494c579b16c2bccacc7401e8dbf29dcf594a7c48...7bb38c36258dfd5aa811be295d5b99a00b9acfac -- View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/494c579b16c2bccacc7401e8dbf29dcf594a7c48...7bb38c36258dfd5aa811be295d5b99a00b9acfac You're receiving this email because of your account on salsa.debian.org.
