Control: tags 756827 + patch Control: forwarded 756827 https://sourceforge.net/p/urjtag/bugs/119/
Dear maintainer, I've prepared an NMU for urjtag (versioned as 0.10+r2007-1.2) and attached the resulting diff to this bug. Since I'm not a DD, I can't upload it myself. If it's OK with you, I'll look for a sponsor in about a week. Feel free to tell me if you want to upload a fix yourself. Regards. -- PGP-encrypted mails preferred PGP Fingerprint: 74CD D9FE 5BCB FE0D 13EE 8EEA 61F3 4426 74DE 6624
diff -Nru urjtag-0.10+r2007/debian/changelog urjtag-0.10+r2007/debian/changelog --- urjtag-0.10+r2007/debian/changelog 2014-07-28 07:40:24.000000000 +0000 +++ urjtag-0.10+r2007/debian/changelog 2014-09-12 18:46:22.000000000 +0000 @@ -1,3 +1,13 @@ +urjtag (0.10+r2007-1.2) UNRELEASED; urgency=medium + + * Non-maintainer upload. + * debian/patches/0010_prefix_REG.patch: (Closes: #756827) + - Prefix all REG_* with BFIN_REG to not clash with enumerators defined in + /usr/include/sys/ucontext.h, this fixes + FTBFS: error: redeclaration of enumerator 'REG_R0' + + -- Andreas Moog <andreas.m...@warperbbs.de> Fri, 12 Sep 2014 20:43:07 +0200 + urjtag (0.10+r2007-1.1) unstable; urgency=medium * Non-maintainer upload. diff -Nru urjtag-0.10+r2007/debian/patches/0010_prefix_REG.patch urjtag-0.10+r2007/debian/patches/0010_prefix_REG.patch --- urjtag-0.10+r2007/debian/patches/0010_prefix_REG.patch 1970-01-01 00:00:00.000000000 +0000 +++ urjtag-0.10+r2007/debian/patches/0010_prefix_REG.patch 2014-09-13 18:53:26.000000000 +0000 @@ -0,0 +1,304 @@ +Description: Prefix all REG_* with BFIN_REG to not clash with enumerators defined in + /usr/include/sys/ucontext.h, this fixes FTBFS: error: redeclaration of enumerator 'REG_R0' +Author: Andreas Moog <andreas.m...@warperbbs.de> +Bug: https://sourceforge.net/p/urjtag/bugs/119/ +Bug-Debian: https://bugs.debian.org/756827 +Forwarded: yes, https://sourceforge.net/p/urjtag/bugs/119/attachment/0010_prefix_REG.patch +Index: urjtag-0.10+r2007/include/urjtag/bfin.h +=================================================================== +--- urjtag-0.10+r2007.orig/include/urjtag/bfin.h ++++ urjtag-0.10+r2007/include/urjtag/bfin.h +@@ -27,35 +27,35 @@ + + + /* High-Nibble: group code, low nibble: register code. */ +-#define T_REG_R 0x00 +-#define T_REG_P 0x10 +-#define T_REG_I 0x20 +-#define T_REG_B 0x30 +-#define T_REG_L 0x34 +-#define T_REG_M 0x24 +-#define T_REG_A 0x40 ++#define T_BFIN_REG_R 0x00 ++#define T_BFIN_REG_P 0x10 ++#define T_BFIN_REG_I 0x20 ++#define T_BFIN_REG_B 0x30 ++#define T_BFIN_REG_L 0x34 ++#define T_BFIN_REG_M 0x24 ++#define T_BFIN_REG_A 0x40 + + enum core_regnum + { +- REG_R0 = T_REG_R, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, +- REG_P0 = T_REG_P, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +- REG_I0 = T_REG_I, REG_I1, REG_I2, REG_I3, +- REG_M0 = T_REG_M, REG_M1, REG_M2, REG_M3, +- REG_B0 = T_REG_B, REG_B1, REG_B2, REG_B3, +- REG_L0 = T_REG_L, REG_L1, REG_L2, REG_L3, +- REG_A0x = T_REG_A, REG_A0w, REG_A1x, REG_A1w, +- REG_ASTAT = 0x46, +- REG_RETS = 0x47, +- REG_LC0 = 0x60, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, +- REG_CYCLES, REG_CYCLES2, +- REG_USP = 0x70, REG_SEQSTAT, REG_SYSCFG, +- REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, ++ BFIN_REG_R0 = T_BFIN_REG_R, BFIN_REG_R1, BFIN_REG_R2, BFIN_REG_R3, BFIN_REG_R4, BFIN_REG_R5, BFIN_REG_R6, BFIN_REG_R7, ++ BFIN_REG_P0 = T_BFIN_REG_P, BFIN_REG_P1, BFIN_REG_P2, BFIN_REG_P3, BFIN_REG_P4, BFIN_REG_P5, BFIN_REG_SP, BFIN_REG_FP, ++ BFIN_REG_I0 = T_BFIN_REG_I, BFIN_REG_I1, BFIN_REG_I2, BFIN_REG_I3, ++ BFIN_REG_M0 = T_BFIN_REG_M, BFIN_REG_M1, BFIN_REG_M2, BFIN_REG_M3, ++ BFIN_REG_B0 = T_BFIN_REG_B, BFIN_REG_B1, BFIN_REG_B2, BFIN_REG_B3, ++ BFIN_REG_L0 = T_BFIN_REG_L, BFIN_REG_L1, BFIN_REG_L2, BFIN_REG_L3, ++ BFIN_REG_A0x = T_BFIN_REG_A, BFIN_REG_A0w, BFIN_REG_A1x, BFIN_REG_A1w, ++ BFIN_REG_ASTAT = 0x46, ++ BFIN_REG_RETS = 0x47, ++ BFIN_REG_LC0 = 0x60, BFIN_REG_LT0, BFIN_REG_LB0, BFIN_REG_LC1, BFIN_REG_LT1, BFIN_REG_LB1, ++ BFIN_REG_CYCLES, BFIN_REG_CYCLES2, ++ BFIN_REG_USP = 0x70, BFIN_REG_SEQSTAT, BFIN_REG_SYSCFG, ++ BFIN_REG_RETI, BFIN_REG_RETX, BFIN_REG_RETN, BFIN_REG_RETE, BFIN_REG_EMUDAT, + }; + + #define CLASS_MASK 0xf0 + #define GROUP(x) (((x) & CLASS_MASK) >> 4) +-#define DREG_P(x) (((x) & CLASS_MASK) == T_REG_R) +-#define PREG_P(x) (((x) & CLASS_MASK) == T_REG_P) ++#define DREG_P(x) (((x) & CLASS_MASK) == T_BFIN_REG_R) ++#define PREG_P(x) (((x) & CLASS_MASK) == T_BFIN_REG_P) + + + #define DTEST_COMMAND 0xffe00300 +Index: urjtag-0.10+r2007/src/bfin/bfin.c +=================================================================== +--- urjtag-0.10+r2007.orig/src/bfin/bfin.c ++++ urjtag-0.10+r2007/src/bfin/bfin.c +@@ -815,17 +815,17 @@ part_register_get (urj_chain_t *chain, i + uint32_t r0 = 0; + + if (DREG_P (reg) || PREG_P (reg)) +- part_emuir_set (chain, n, gen_move (REG_EMUDAT, reg), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_move (BFIN_REG_EMUDAT, reg), URJ_CHAIN_EXITMODE_IDLE); + else + { +- r0 = part_register_get (chain, n, REG_R0); ++ r0 = part_register_get (chain, n, BFIN_REG_R0); + + part_scan_select (chain, n, DBGCTL_SCAN); + part_dbgctl_bit_set_emuirlpsz_2 (chain, n); + urj_tap_chain_shift_data_registers_mode (chain, 0, 1, URJ_CHAIN_EXITMODE_UPDATE); + +- part_emuir_set_2 (chain, n, gen_move (REG_R0, reg), +- gen_move (REG_EMUDAT, REG_R0), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set_2 (chain, n, gen_move (BFIN_REG_R0, reg), ++ gen_move (BFIN_REG_EMUDAT, BFIN_REG_R0), URJ_CHAIN_EXITMODE_IDLE); + + part_scan_select (chain, n, DBGCTL_SCAN); + part_dbgctl_bit_clear_emuirlpsz_2 (chain, n); +@@ -838,7 +838,7 @@ part_register_get (urj_chain_t *chain, i + r = part->active_instruction->data_register->out; + + if (!DREG_P (reg) && !PREG_P (reg)) +- part_register_set (chain, n, REG_R0, r0); ++ part_register_set (chain, n, BFIN_REG_R0, r0); + + return emudat_value (r); + } +@@ -851,7 +851,7 @@ part_register_set (urj_chain_t *chain, i + uint32_t r0 = 0; + + if (!DREG_P (reg) && !PREG_P (reg)) +- r0 = part_register_get (chain, n, REG_R0); ++ r0 = part_register_get (chain, n, BFIN_REG_R0); + + part_scan_select (chain, n, EMUDAT_SCAN); + +@@ -863,46 +863,46 @@ part_register_set (urj_chain_t *chain, i + urj_tap_chain_shift_data_registers_mode (chain, 0, 1, URJ_CHAIN_EXITMODE_UPDATE); + + if (DREG_P (reg) || PREG_P (reg)) +- part_emuir_set (chain, n, gen_move (reg, REG_EMUDAT), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_move (reg, BFIN_REG_EMUDAT), URJ_CHAIN_EXITMODE_IDLE); + else + { + part_scan_select (chain, n, DBGCTL_SCAN); + part_dbgctl_bit_set_emuirlpsz_2 (chain, n); + urj_tap_chain_shift_data_registers_mode (chain, 0, 1, URJ_CHAIN_EXITMODE_UPDATE); + +- part_emuir_set_2 (chain, n, gen_move (REG_R0, REG_EMUDAT), +- gen_move (reg, REG_R0), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set_2 (chain, n, gen_move (BFIN_REG_R0, BFIN_REG_EMUDAT), ++ gen_move (reg, BFIN_REG_R0), URJ_CHAIN_EXITMODE_IDLE); + + part_scan_select (chain, n, DBGCTL_SCAN); + part_dbgctl_bit_clear_emuirlpsz_2 (chain, n); + urj_tap_chain_shift_data_registers_mode (chain, 0, 1, URJ_CHAIN_EXITMODE_UPDATE); + +- part_register_set (chain, n, REG_R0, r0); ++ part_register_set (chain, n, BFIN_REG_R0, r0); + } + } + + uint32_t + part_get_r0 (urj_chain_t *chain, int n) + { +- return part_register_get (chain, n, REG_R0); ++ return part_register_get (chain, n, BFIN_REG_R0); + } + + uint32_t + part_get_p0 (urj_chain_t *chain, int n) + { +- return part_register_get (chain, n, REG_P0); ++ return part_register_get (chain, n, BFIN_REG_P0); + } + + void + part_set_r0 (urj_chain_t *chain, int n, uint32_t value) + { +- part_register_set (chain, n, REG_R0, value); ++ part_register_set (chain, n, BFIN_REG_R0, value); + } + + void + part_set_p0 (urj_chain_t *chain, int n, uint32_t value) + { +- part_register_set (chain, n, REG_P0, value); ++ part_register_set (chain, n, BFIN_REG_P0, value); + } + + void +@@ -995,7 +995,7 @@ chain_system_reset (urj_chain_t *chain) + /* Write 0x7 to SWRST to start system reset. */ + part_set_p0 (chain, chain->main_part, SWRST); + part_set_r0 (chain, chain->main_part, 0x7); +- part_emuir_set (chain, chain->main_part, gen_store16_offset (REG_P0, 0, REG_R0), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, chain->main_part, gen_store16_offset (BFIN_REG_P0, 0, BFIN_REG_R0), URJ_CHAIN_EXITMODE_IDLE); + + /* + * Delay at least 10 SCLKs instead of doing an SSYNC insn. +@@ -1008,7 +1008,7 @@ chain_system_reset (urj_chain_t *chain) + + /* Write 0x0 to SWRST to stop system reset. */ + part_set_r0 (chain, chain->main_part, 0); +- part_emuir_set (chain, chain->main_part, gen_store16_offset (REG_P0, 0, REG_R0), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, chain->main_part, gen_store16_offset (BFIN_REG_P0, 0, BFIN_REG_R0), URJ_CHAIN_EXITMODE_IDLE); + + /* Delay at least 1 SCLK; see comment above for more info. */ + usleep (100); +@@ -1058,14 +1058,14 @@ part_emupc_reset (urj_chain_t *chain, in + urj_part_t *part = chain->parts->parts[n]; + uint32_t p0; + +- p0 = part_register_get (chain, n, REG_P0); ++ p0 = part_register_get (chain, n, BFIN_REG_P0); + + BFIN_PART_EMUPC (part) = new_pc; + +- part_register_set (chain, n, REG_P0, new_pc); +- part_emuir_set (chain, n, gen_jump_reg (REG_P0), URJ_CHAIN_EXITMODE_IDLE); ++ part_register_set (chain, n, BFIN_REG_P0, new_pc); ++ part_emuir_set (chain, n, gen_jump_reg (BFIN_REG_P0), URJ_CHAIN_EXITMODE_IDLE); + +- part_register_set (chain, n, REG_P0, p0); ++ part_register_set (chain, n, BFIN_REG_P0, p0); + } + + uint32_t +@@ -1083,22 +1083,22 @@ part_mmr_read_clobber_r0 (urj_chain_t *c + + if (size == 2) + part_emuir_set_2 (chain, n, +- gen_load16z (REG_R0, REG_P0), +- gen_move (REG_EMUDAT, REG_R0), ++ gen_load16z (BFIN_REG_R0, BFIN_REG_P0), ++ gen_move (BFIN_REG_EMUDAT, BFIN_REG_R0), + URJ_CHAIN_EXITMODE_UPDATE); + else + part_emuir_set_2 (chain, n, +- gen_load32 (REG_R0, REG_P0), +- gen_move (REG_EMUDAT, REG_R0), ++ gen_load32 (BFIN_REG_R0, BFIN_REG_P0), ++ gen_move (BFIN_REG_EMUDAT, BFIN_REG_R0), + URJ_CHAIN_EXITMODE_UPDATE); + } + else + { + if (size == 2) +- part_emuir_set (chain, n, gen_load16z_offset (REG_R0, REG_P0, offset), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_load16z_offset (BFIN_REG_R0, BFIN_REG_P0, offset), URJ_CHAIN_EXITMODE_IDLE); + else +- part_emuir_set (chain, n, gen_load32_offset (REG_R0, REG_P0, offset), URJ_CHAIN_EXITMODE_IDLE); +- part_emuir_set (chain, n, gen_move (REG_EMUDAT, REG_R0), URJ_CHAIN_EXITMODE_UPDATE); ++ part_emuir_set (chain, n, gen_load32_offset (BFIN_REG_R0, BFIN_REG_P0, offset), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_move (BFIN_REG_EMUDAT, BFIN_REG_R0), URJ_CHAIN_EXITMODE_UPDATE); + } + value = part_emudat_get (chain, n, URJ_CHAIN_EXITMODE_IDLE); + +@@ -1118,14 +1118,14 @@ part_mmr_read (urj_chain_t *chain, int n + uint32_t p0, r0; + uint32_t value; + +- p0 = part_register_get (chain, n, REG_P0); +- r0 = part_register_get (chain, n, REG_R0); ++ p0 = part_register_get (chain, n, BFIN_REG_P0); ++ r0 = part_register_get (chain, n, BFIN_REG_R0); + +- part_register_set (chain, n, REG_P0, addr); ++ part_register_set (chain, n, BFIN_REG_P0, addr); + value = part_mmr_read_clobber_r0 (chain, n, 0, size); + +- part_register_set (chain, n, REG_P0, p0); +- part_register_set (chain, n, REG_R0, r0); ++ part_register_set (chain, n, BFIN_REG_P0, p0); ++ part_register_set (chain, n, BFIN_REG_R0, r0); + + return value; + } +@@ -1145,22 +1145,22 @@ part_mmr_write_clobber_r0 (urj_chain_t * + + if (size == 2) + part_emuir_set_2 (chain, n, +- gen_move (REG_R0, REG_EMUDAT), +- gen_store16 (REG_P0, REG_R0), ++ gen_move (BFIN_REG_R0, BFIN_REG_EMUDAT), ++ gen_store16 (BFIN_REG_P0, BFIN_REG_R0), + URJ_CHAIN_EXITMODE_IDLE); + else + part_emuir_set_2 (chain, n, +- gen_move (REG_R0, REG_EMUDAT), +- gen_store32 (REG_P0, REG_R0), ++ gen_move (BFIN_REG_R0, BFIN_REG_EMUDAT), ++ gen_store32 (BFIN_REG_P0, BFIN_REG_R0), + URJ_CHAIN_EXITMODE_IDLE); + } + else + { +- part_emuir_set (chain, n, gen_move (REG_R0, REG_EMUDAT), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_move (BFIN_REG_R0, BFIN_REG_EMUDAT), URJ_CHAIN_EXITMODE_IDLE); + if (size == 2) +- part_emuir_set (chain, n, gen_store16_offset (REG_P0, offset, REG_R0), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_store16_offset (BFIN_REG_P0, offset, BFIN_REG_R0), URJ_CHAIN_EXITMODE_IDLE); + else +- part_emuir_set (chain, n, gen_store32_offset (REG_P0, offset, REG_R0), URJ_CHAIN_EXITMODE_IDLE); ++ part_emuir_set (chain, n, gen_store32_offset (BFIN_REG_P0, offset, BFIN_REG_R0), URJ_CHAIN_EXITMODE_IDLE); + } + + if (offset == 0) +@@ -1176,14 +1176,14 @@ part_mmr_write (urj_chain_t *chain, int + { + uint32_t p0, r0; + +- p0 = part_register_get (chain, n, REG_P0); +- r0 = part_register_get (chain, n, REG_R0); ++ p0 = part_register_get (chain, n, BFIN_REG_P0); ++ r0 = part_register_get (chain, n, BFIN_REG_R0); + +- part_register_set (chain, n, REG_P0, addr); ++ part_register_set (chain, n, BFIN_REG_P0, addr); + part_mmr_write_clobber_r0 (chain, n, 0, data, size); + +- part_register_set (chain, n, REG_P0, p0); +- part_register_set (chain, n, REG_R0, r0); ++ part_register_set (chain, n, BFIN_REG_P0, p0); ++ part_register_set (chain, n, BFIN_REG_R0, r0); + } + + struct bfin_part_data bfin_part_data_initializer = diff -Nru urjtag-0.10+r2007/debian/patches/series urjtag-0.10+r2007/debian/patches/series --- urjtag-0.10+r2007/debian/patches/series 2014-07-28 07:40:24.000000000 +0000 +++ urjtag-0.10+r2007/debian/patches/series 2014-09-12 19:07:44.000000000 +0000 @@ -1,2 +1,3 @@ 10_disable_lib.patch fix-build-bison3.patch +0010_prefix_REG.patch
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