Will try tomorrow. I'm currently using patch https://bugs.freedesktop.org/attachment.cgi?id=52762 from https://bugs.freedesktop.org/show_bug.cgi?id=40221 applied on top of vanilla 3.1 kernel. It works fine.
Your patch is a bit different in code, so I need to check it. Will check using Debian 3.1 kernel. -- Best regards, Valentyn Pavliuchenko 2011/12/22 Jonathan Nieder <jrnie...@gmail.com> > found 646376 linux-2.6/3.0.0-3 > tags 646376 + upstream patch moreinfo > quit > > Michel Dänzer wrote: > > Valentyn Pavliuchenko wrote: > > >> I have ATI Cayman (Radeon HD 6790). When working with a PC for for an > hour I > >> got corruption of different parts of screen (like windows captions, > menus, > >> whole windows, window shadows, etc.). The corruption looks like using > >> uninitializaed memory instead of textures. After reboot everything is > ok. > > > > See the upstream bug report referenced above. Looks like it's finally > > about to be fixed. > > Thanks, Michel. > > Valentyn, could you try this patch and see if helps? [1] has > instructions. > > [1] http://kernel-handbook.alioth.debian.org/ch-common-tasks.html > > From: Jerome Glisse <jgli...@redhat.com> > Date: Wed, 26 Oct 2011 11:41:22 -0400 > Subject: drm/radeon: flush read cache for gtt with fence on r6xx and newer > GPU V3 > > commit 77b1bad423599c9841ea282a82172f039bb2ff92 upstream. > > Cayman seems to be particularly sensitive to read cache returning > old data after bind/unbind to GTT. Flush read cache for GTT range > with each fences for all new hw. Should fix several rendering glitches. > Like > > V2 flush whole address space > V3 also flush shader read cache > > https://bugs.freedesktop.org/show_bug.cgi?id=40221 > https://bugs.freedesktop.org/show_bug.cgi?id=38022 > https://bugzilla.redhat.com/show_bug.cgi?id=738790 > > Signed-off-by: Jerome Glisse <jgli...@redhat.com> > Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> > Signed-off-by: Dave Airlie <airl...@redhat.com> > Signed-off-by: Jonathan Nieder <jrnie...@gmail.com> > --- > drivers/gpu/drm/radeon/evergreen_blit_kms.c | 4 ++-- > drivers/gpu/drm/radeon/r600.c | 16 ++++++++++++++++ > drivers/gpu/drm/radeon/r600_blit_kms.c | 4 ++-- > 3 files changed, 20 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c > b/drivers/gpu/drm/radeon/evergreen_blit_kms.c > index 2eb251858e72..80ef4401ee9e 100644 > --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c > +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c > @@ -779,9 +779,9 @@ int evergreen_blit_prepare_copy(struct radeon_device > *rdev, int size_bytes) > ring_size = num_loops * dwords_per_loop; > /* set default + shaders */ > ring_size += 55; /* shaders + def state */ > - ring_size += 10; /* fence emit for VB IB */ > + ring_size += 16; /* fence emit for VB IB */ > ring_size += 5; /* done copy */ > - ring_size += 10; /* fence emit for done copy */ > + ring_size += 16; /* fence emit for done copy */ > r = radeon_ring_lock(rdev, ring_size); > if (r) > return r; > diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c > index 9b62a97742a7..0991e63191c8 100644 > --- a/drivers/gpu/drm/radeon/r600.c > +++ b/drivers/gpu/drm/radeon/r600.c > @@ -2327,6 +2327,14 @@ void r600_fence_ring_emit(struct radeon_device > *rdev, > if (rdev->wb.use_event) { > u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + > (u64)(rdev->fence_drv.scratch_reg - > rdev->scratch.reg_base); > + /* flush read cache over gart */ > + radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); > + radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | > + PACKET3_VC_ACTION_ENA | > + PACKET3_SH_ACTION_ENA); > + radeon_ring_write(rdev, 0xFFFFFFFF); > + radeon_ring_write(rdev, 0); > + radeon_ring_write(rdev, 10); /* poll interval */ > /* EVENT_WRITE_EOP - flush caches, send int */ > radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, > 4)); > radeon_ring_write(rdev, > EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); > @@ -2335,6 +2343,14 @@ void r600_fence_ring_emit(struct radeon_device > *rdev, > radeon_ring_write(rdev, fence->seq); > radeon_ring_write(rdev, 0); > } else { > + /* flush read cache over gart */ > + radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); > + radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | > + PACKET3_VC_ACTION_ENA | > + PACKET3_SH_ACTION_ENA); > + radeon_ring_write(rdev, 0xFFFFFFFF); > + radeon_ring_write(rdev, 0); > + radeon_ring_write(rdev, 10); /* poll interval */ > radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); > radeon_ring_write(rdev, > EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); > /* wait for 3D idle clean */ > diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c > b/drivers/gpu/drm/radeon/r600_blit_kms.c > index 9aa74c3f8cb6..d198b89cd403 100644 > --- a/drivers/gpu/drm/radeon/r600_blit_kms.c > +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c > @@ -632,9 +632,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, > int size_bytes) > ring_size = num_loops * dwords_per_loop; > /* set default + shaders */ > ring_size += 40; /* shaders + def state */ > - ring_size += 10; /* fence emit for VB IB */ > + ring_size += 16; /* fence emit for VB IB */ > ring_size += 5; /* done copy */ > - ring_size += 10; /* fence emit for done copy */ > + ring_size += 16; /* fence emit for done copy */ > r = radeon_ring_lock(rdev, ring_size); > if (r) > return r; > -- > 1.7.8 > >
