On 2005-04-21 23:47:13 +0200, maximilian attems wrote:
> please send in the output of lspci -vv on your box?

0000:00:0b.0 Host bridge: Apple Computer Inc. UniNorth AGP
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort+ >SERR- <PERR-
        Latency: 16, Cache Line Size: 0x08 (32 bytes)
        Capabilities: <available only to root>

0000:00:10.0 VGA compatible controller: ATI Technologies Inc Rage Mobility M3 
AGP 2x (rev 02) (prog-if 00 [VGA])
        Subsystem: ATI Technologies Inc Rage Mobility M3 AGP 2x
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping+ SERR- FastB2B-
        Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 255 (2000ns min), Cache Line Size: 0x08 (32 bytes)
        Interrupt: pin A routed to IRQ 48
        Region 0: Memory at a4000000 (32-bit, prefetchable) [size=64M]
        Region 1: I/O ports at 802400 [size=256]
        Region 2: Memory at a0000000 (32-bit, non-prefetchable) [size=16K]
        Expansion ROM at f1000000 [disabled] [size=128K]
        Capabilities: <available only to root>

0001:10:0b.0 Host bridge: Apple Computer Inc. UniNorth PCI
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort+ >SERR- <PERR-
        Latency: 16, Cache Line Size: 0x08 (32 bytes)

0001:10:17.0 ff00: Apple Computer Inc. KeyLargo Mac I/O (rev 03)
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 16, Cache Line Size: 0x08 (32 bytes)
        Region 0: Memory at 80000000 (32-bit, non-prefetchable) [size=512K]

0001:10:18.0 USB Controller: Apple Computer Inc. KeyLargo USB (prog-if 10 
[OHCI])
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 16 (750ns min, 21500ns max)
        Interrupt: pin A routed to IRQ 27
        Region 0: Memory at 80082000 (32-bit, non-prefetchable) [size=4K]

0001:10:19.0 USB Controller: Apple Computer Inc. KeyLargo USB (prog-if 10 
[OHCI])
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 16 (750ns min, 21500ns max)
        Interrupt: pin A routed to IRQ 28
        Region 0: Memory at 80081000 (32-bit, non-prefetchable) [size=4K]

0001:10:1a.0 CardBus bridge: Texas Instruments PCI1211
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 168, Cache Line Size: 0x08 (32 bytes)
        Interrupt: pin A routed to IRQ 58
        Region 0: Memory at 80080000 (32-bit, non-prefetchable) [size=4K]
        Bus: primary=10, secondary=11, subordinate=14, sec-latency=176
        Memory window 0: 80400000-807ff000 (prefetchable)
        Memory window 1: f3000000-f31ff000
        I/O window 0: 00001000-000010ff
        I/O window 1: 00001400-000014ff
        BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset+ 16bInt+ PostWrite+
        16-bit legacy interface ports at 0001

0002:24:0b.0 Host bridge: Apple Computer Inc. UniNorth Internal PCI
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort+ >SERR- <PERR-
        Latency: 16, Cache Line Size: 0x08 (32 bytes)

0002:24:0e.0 FireWire (IEEE 1394): Apple Computer Inc. UniNorth FireWire (rev 
01) (prog-if 10 [OHCI])
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 0 (750ns min, 1000ns max), Cache Line Size: 0x08 (32 bytes)
        Interrupt: pin A routed to IRQ 40
        Region 0: Memory at f5000000 (32-bit, non-prefetchable) [size=4K]

0002:24:0f.0 Ethernet controller: Apple Computer Inc. UniNorth GMAC (Sun GEM) 
(rev 01)
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
        Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=slow >TAbort- <TAbort- 
<MAbort- >SERR- <PERR+
        Latency: 16 (16000ns min, 16000ns max), Cache Line Size: 0x08 (32 bytes)
        Interrupt: pin A routed to IRQ 41
        Region 0: Memory at f5200000 (32-bit, non-prefetchable) [size=2M]
        Expansion ROM at f5100000 [disabled] [size=1M]

-- 
Vincent Lefèvre <[EMAIL PROTECTED]> - Web: <http://www.vinc17.org/>
100% accessible validated (X)HTML - Blog: <http://www.vinc17.org/blog/>
Work: CR INRIA - computer arithmetic / SPACES project at LORIA


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