Package: make
Version: 3.81
If I do:
define variable
line1
line2
line3
...
endef
target:
$(shell $(variable))
then make 3.80 does this
sh -c line1 line2 line3 ...
which while not exactly ideal is at least useable.
make 3.81 does this
sh -c "line1line2line3 ..."
which is just insane.
This incompatible change isn't even mandated by POSIX because in POSIX
there are no multi-line variables. Furthermore, it breaks my
makefile and leaves me with no workaround as far as I can tell.
The makefile I have and which works with 3.80 works around the lack of
a proper macro language in make like this (fragment of a file called
manypics.make):
define makesubmakefile
set -e; d=.submakefile.new; rm -f $$d; for f in "$$@";do echo "$$f" >>$$d;
done
--
$(foreach prog, $(PROGRAMS), $(call define_prog,$(prog)))
$(foreach da, idlocs% config %+morse %+pindata blank%,
$(call define_directasm,$(da)))
endef
.submakefile: manypics.make Makefile
: $(shell $(makesubmakefile)) ... generate .submakefile
@mv -f [EMAIL PROTECTED] $@
ifneq ($(MAKECMDGOALS),clean)
include .submakefile
endif
I am really very angry about these recent behavioural changes in make.
The documentation for GNU make has never been sufficient to predict
accurately the quoting behaviour; therefore a generation of
programmers have used experimentation to decide how they need to write
their makefiles. It is quite unreasonable now to decide that the
behaviour, which everyone may not have liked at the time but is now
relying on, is undesirable.
Ian.
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