On Tue, 31 Mar 2026 15:09:34 +0200 Lukas Wunner <[email protected]> wrote:
> On Mon, Mar 30, 2026 at 08:14:53AM +0200, Bernd Schumacher wrote: > > [ 0.318903] pci 0000:07:00.0: [dd01:0003] type 00 class 0x048000 PCIe > > Endpoint > > [ 0.318939] pci 0000:07:00.0: BAR 0 [mem > > 0xfffffffffc500000-0xfffffffffc50ffff 64bit] > > BIOS initially sets the BAR address to an incorrect value (the top 32 bits > should be all zeroes instead of all ones)... > > > [ 0.339685] pci 0000:07:00.0: BAR 0 [mem > > 0xfffffffffc500000-0xfffffffffc50ffff 64bit]: can't claim; no compatible > > bridge window > [...] > > [ 0.311065] pci 0000:02:03.0: [1022:57a3] type 01 class 0x060400 PCIe > > Switch Downstream Port > > [ 0.311107] pci 0000:02:03.0: PCI bridge to [bus 07] > > [ 0.311118] pci 0000:02:03.0: bridge window [mem > > 0xfc500000-0xfc5fffff] > > ... this doesn't fit into the window of the bridge above the DVB card, > which has the top 32 bits set to all zeroes... > > > [ 0.357346] pci 0000:07:00.0: BAR 0 [mem 0xfc500000-0xfc50ffff 64bit]: > > assigned > > ... the kernel fixes the incorrect BAR, but it seems there's an ordering > issue such that pci_save_state() is called beforehand. It's weird that > this doen't occur with newer kernels and it would be good to understand why. > I'm not seeing the ordering issue despite staring at the code for a while. Do we know this isn't occurring on newer kernels? If we have a bogus BAR address that later gets fixed, this seems like a fairly unique setup. AIUI, we're saving the state via the call chain invoked by subsys_initcall(pcibios_init), but I think we're doing the resource fixes in fs_initcall(pcibios_assign_resources). That suggests that the saved state would have the bogus BAR values. If we toss PM runtime into that mix, pci_pm_default_resume_early() will call pci_restore_state() however pci_save_state() in that file is mostly wrapped around pci_dev->state_saved guards. This suggests we likely won't save the reallocated state, but we will restore the pre-reallocated state. Maybe this can be quickly validated by loading vfio-pci with the disable_idle_d3=1 option to avoid the PM transition. Thanks, Alex
