Source: sphde
Followup-For: Bug #1059602
X-Debbugs-Cc: debian-loonga...@lists.debian.org
Dear Maintainer,
Make a patch based on the upstream merged PR and pass the local test
wuruilong
--- /dev/null
+++ sphde-1.4.0/ChangeLog.md
@@ -0,0 +1 @@
+# ChangeLog
--- sphde-1.4.0.orig/config.sub
+++ sphde-1.4.0/config.sub
@@ -268,6 +268,7 @@ case $basic_machine in
| k1om \
| le32 | le64 \
| lm32 \
+ | loongarch \
| m32c | m32r | m32rle | m68000 | m68k | m88k \
| maxq | mb | microblaze | microblazeel | mcore | mep | metag \
| mips | mipsbe | mipseb | mipsel | mipsle \
--- sphde-1.4.0.orig/src/sasatom.h
+++ sphde-1.4.0/src/sasatom.h
@@ -41,6 +41,8 @@ typedef void* sas_lock_ptr_t;
#include "sasatom_x86_64.h"
#elif defined(__i386__)
#include "sasatom_i386.h"
+#elif defined(__loongarch__)
+#include "sasatom_loongarch.h"
#else
#include "sasatom_generic.h"
#endif
--- /dev/null
+++ sphde-1.4.0/src/sasatom_loongarch.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 1995-2014 IBM Corporation.
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ */
+
+#ifndef _SASATOMIC_LOONGARCH_H
+#define _SASATOMIC_LOONGARCH_H
+
+#define __arch_sas_write_barrier() __sync_synchronize()
+#define __arch_sas_read_barrier() __sync_synchronize()
+#define __arch_sas_full_barrier() __sync_synchronize()
+
+static inline void
+__arch_pause (void)
+{
+ __asm__ (
+ " nop;"
+ :
+ :
+ : "memory"
+ );
+}
+
+#if GCC_VERSION >= 40700
+static inline void *
+__arch_fetch_and_add_ptr(void **pointer, long int delta)
+{
+ return __atomic_fetch_add (pointer, delta, __ATOMIC_RELAXED);
+}
+#else
+static inline void *
+__arch_fetch_and_add_ptr(void **pointer, long int delta)
+{
+ return (void*)__sync_fetch_and_add((long int*)*pointer, delta);
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline long int
+__arch_fetch_and_add(long int *pointer, long int delta)
+{
+ return __atomic_fetch_add (pointer, delta, __ATOMIC_RELAXED);
+}
+#else
+static inline long int
+__arch_fetch_and_add(void *pointer, long int delta)
+{
+ return __sync_fetch_and_add((long int*)pointer, delta);
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline int
+__arch_compare_and_swap (volatile long int *pointer,
+ long int oldval, long int newval)
+{
+ long int temp = oldval;
+ return __atomic_compare_exchange_n (pointer, &temp, newval, 1,
__ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
+}
+#else
+static inline int
+__arch_compare_and_swap (volatile long int *p, long int oldval, long int
newval)
+{
+ return __sync_val_compare_and_swap(p, oldval, newval);
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline long int
+__arch_atomic_swap (long int *pointer, long int replace)
+{
+ return __atomic_exchange_n (pointer, replace, __ATOMIC_RELAXED);
+}
+#else
+static inline long int __arch_atomic_swap(long int *p, long int replace)
+{
+ long temp = *p;
+ int success = 0;
+ //*p = replace;
+ do {
+ temp = *p;
+ success = __sync_bool_compare_and_swap (p, temp, replace);
+ }while (!success);
+
+ return temp;
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline void
+__arch_atomic_inc(long int *pointer)
+{
+ const long int inc_val = 1L;
+
+ __atomic_fetch_add (pointer, inc_val, __ATOMIC_RELAXED);
+}
+#else
+static inline void
+__arch_atomic_inc (long int *pointer)
+{
+ const long int inc_val = 1L;
+ //(*p)++;
+ __sync_fetch_and_add (pointer, inc_val);
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline void
+__arch_atomic_dec(long int *pointer)
+{
+ const long int inc_val = -1L;
+
+ __atomic_fetch_add (pointer, inc_val, __ATOMIC_RELAXED);
+}
+#else
+static inline void
+__arch_atomic_dec (long int *pointer)
+{
+ const long int inc_val = -1L;
+ //(*p)--;
+ __sync_fetch_and_add (pointer, inc_val);
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline void
+__arch_sas_spin_lock (volatile sas_spin_lock_t *lock)
+{
+ int oldval = 0;
+ int newval = 1;
+ int success = 0;
+
+ do {
+ success = __atomic_compare_exchange_n (lock, &oldval, newval, 1,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
+ } while (!success);
+}
+#else
+static inline void
+__arch_sas_spin_lock (volatile sas_spin_lock_t *lock)
+{
+ int oldval = 0;
+ int newval = 1;
+ int success = 0;
+
+ do {
+ success = __sync_bool_compare_and_swap (lock, oldval, newval);
+ } while (!success);
+}
+#endif
+
+#if GCC_VERSION >= 40700
+static inline int
+__arch_sas_spin_trylock (volatile sas_spin_lock_t *lock)
+{
+ int oldval = 0;
+ int newval = 1;
+ int success = 0;
+
+ success = __atomic_compare_exchange_n (lock, &oldval, newval, 1,
+ __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
+
+ return (!success);
+}
+#else
+static inline int
+__arch_sas_spin_trylock (volatile sas_spin_lock_t *lock)
+{
+ int oldval = 0;
+ int newval = 1;
+ int success;
+
+ success = __sync_bool_compare_and_swap (lock, oldval, newval);
+
+ return (!success);
+}
+#endif
+#endif // _SASATOMIC_LOONGARCH_H
--- sphde-1.4.0.orig/src/sasconf.h
+++ sphde-1.4.0/src/sasconf.h
@@ -108,6 +108,14 @@
# endif
#endif
+#ifdef __loongarch__
+# define __WORDSIZE_64
+# define __SAS_BASE_ADDRESS 0x4000000000L
+# define RegionSize 0x2000000000L /* 128GB */
+# define SegmentSize 0x0010000000L /* 256MB */
+# define __SAS_SHMAP_MAX 0x0001000000L /* 16MB */
+#endif
+
/*
* If the platform is not recognized above, select some resonable default.
*/
--- sphde-1.4.0.orig/src/sassim.cpp
+++ sphde-1.4.0/src/sassim.cpp
@@ -125,7 +125,8 @@ typedef struct
#if defined (__x86_64__) || \
(defined (__LITTLE_ENDIAN__) && defined (__powerpc64__)) \
|| defined (__aarch64__) || defined (__arm__) \
- || ((__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) && defined(__mips64))
+ || ((__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) && defined(__mips64)) \
+ || defined (__loongarch__)
unsigned long offset:56;
unsigned int size:8;
#else
