Source: sparse Version: 0.6.4-4 Followup-For: Bug #1071605 X-Debbugs-Cc: wuruil...@loongson.cn
Dear Maintainer, Thank you for providing the address. I read Dan Carpenter's code review comments and made changes accordingly. I've provided a new patch under this bug; since I haven't sent a patch to lore.kernel.org, I will try to send it upstream and may need your help if there are problems. Good luck! wuruilong
Description: <short summary of the patch> TODO: Put a short summary on the line above and replace this paragraph with a longer explanation of this change. Complete the meta-information with other relevant fields (see below for details). To make it easier, the information below has been extracted from the changelog. Adjust it or drop it. . sparse (0.6.4-4) unstable; urgency=medium . * Disable llvm support as it fails to compile with llvm >= 16 (Closes: #1051864) * Switch to gcc-13 * Bump Standards-Version (no changes required) Author: Uwe Kleine-König <uklei...@debian.org> Bug-Debian: https://bugs.debian.org/1051864 --- The information above should follow the Patch Tagging Guidelines, please checkout https://dep.debian.net/deps/dep3/ to learn about the format. Here are templates for supplementary fields that you might want to add: Origin: (upstream|backport|vendor|other), (<patch-url>|commit:<commit-id>) Bug: <upstream-bugtracker-url> Bug-Debian: https://bugs.debian.org/<bugnumber> Bug-Ubuntu: https://launchpad.net/bugs/<bugnumber> Forwarded: (no|not-needed|<patch-forwarded-url>) Applied-Upstream: <version>, (<commit-url>|commit:<commid-id>) Reviewed-By: <name and email of someone who approved/reviewed the patch> Last-Update: 2024-10-23 --- sparse-0.6.4.orig/Makefile +++ sparse-0.6.4/Makefile @@ -74,6 +74,7 @@ LIB_OBJS += target-arm64.o LIB_OBJS += target-bfin.o LIB_OBJS += target-default.o LIB_OBJS += target-h8300.o +LIB_OBJS += target-loongarch64.o LIB_OBJS += target-m68k.o LIB_OBJS += target-microblaze.o LIB_OBJS += target-mips.o --- sparse-0.6.4.orig/machine.h +++ sparse-0.6.4/machine.h @@ -42,6 +42,7 @@ enum machine { MACH_OPENRISC, MACH_SH, MACH_XTENSA, + MACH_LOONGARCH64, MACH_UNKNOWN }; @@ -55,6 +56,8 @@ enum machine { #define MACH_NATIVE MACH_X86_64 #elif defined(__i386__) || defined(__i386) #define MACH_NATIVE MACH_I386 +#elif defined(__loongarch__) +#define MACH_NATIVE MACH_LOONGARCH64 #elif defined(__mips64__) || (defined(__mips) && __mips == 64) #define MACH_NATIVE MACH_MIPS64 #elif defined(__mips__) || defined(__mips) --- /dev/null +++ sparse-0.6.4/target-loongarch64.c @@ -0,0 +1,21 @@ +#include "symbol.h" +#include "target.h" +#include "machine.h" + + + +static void predefine_loongarch64(const struct target *self) +{ + predefine("__loongarch__", 1, "64"); +} + +const struct target target_loongarch64 = { + .mach = MACH_LOONGARCH64, + .bitness = ARCH_LP64, + + .big_endian = 0, + .unsigned_char = 0, + .has_int128 = 1, + + .predefine = predefine_loongarch64, +}; --- sparse-0.6.4.orig/target.c +++ sparse-0.6.4/target.c @@ -94,6 +94,7 @@ static const struct target *targets[] = [MACH_PPC64] = &target_ppc64, [MACH_RISCV32] = &target_riscv32, [MACH_RISCV64] = &target_riscv64, + [MACH_LOONGARCH64] = &target_loongarch64, [MACH_S390] = &target_s390, [MACH_S390X] = &target_s390x, [MACH_SH] = &target_sh, @@ -112,29 +113,30 @@ enum machine target_parse(const char *na enum machine mach; char bits; } archs[] = { - { "alpha", MACH_ALPHA, 64, }, - { "aarch64", MACH_ARM64, 64, }, - { "arm64", MACH_ARM64, 64, }, - { "arm", MACH_ARM, 32, }, - { "bfin", MACH_BFIN, 32, }, - { "h8300", MACH_H8300, 32, }, - { "i386", MACH_I386, 32, }, - { "m68k", MACH_M68K, 32, }, - { "microblaze", MACH_MICROBLAZE,32, }, - { "mips", MACH_MIPS32, 0, }, - { "nds32", MACH_NDS32, 32, }, - { "nios2", MACH_NIOS2, 32, }, - { "openrisc", MACH_OPENRISC, 32, }, - { "powerpc", MACH_PPC32, 0, }, - { "ppc", MACH_PPC32, 0, }, - { "riscv", MACH_RISCV32, 0, }, - { "s390x", MACH_S390X, 64, }, - { "s390", MACH_S390, 32, }, - { "sparc", MACH_SPARC32, 0, }, - { "x86_64", MACH_X86_64, 64, }, - { "x86-64", MACH_X86_64, 64, }, - { "sh", MACH_SH, 32, }, - { "xtensa", MACH_XTENSA, 32, }, + { "alpha", MACH_ALPHA, 64, }, + { "aarch64", MACH_ARM64, 64, }, + { "arm64", MACH_ARM64, 64, }, + { "arm", MACH_ARM, 32, }, + { "bfin", MACH_BFIN, 32, }, + { "h8300", MACH_H8300, 32, }, + { "i386", MACH_I386, 32, }, + { "loongarch64", MACH_LOONGARCH64, 64, }, + { "m68k", MACH_M68K, 32, }, + { "microblaze", MACH_MICROBLAZE, 32, }, + { "mips", MACH_MIPS32, 0, }, + { "nds32", MACH_NDS32, 32, }, + { "nios2", MACH_NIOS2, 32, }, + { "openrisc", MACH_OPENRISC, 32, }, + { "powerpc", MACH_PPC32, 0, }, + { "ppc", MACH_PPC32, 0, }, + { "riscv", MACH_RISCV32, 0, }, + { "s390x", MACH_S390X, 64, }, + { "s390", MACH_S390, 32, }, + { "sparc", MACH_SPARC32, 0, }, + { "x86_64", MACH_X86_64, 64, }, + { "x86-64", MACH_X86_64, 64, }, + { "sh", MACH_SH, 32, }, + { "xtensa", MACH_XTENSA, 32, }, { NULL }, }; const struct arch *p; --- sparse-0.6.4.orig/target.h +++ sparse-0.6.4/target.h @@ -120,6 +120,7 @@ extern const struct target target_ppc32; extern const struct target target_ppc64; extern const struct target target_riscv32; extern const struct target target_riscv64; +extern const struct target target_loongarch64; extern const struct target target_s390; extern const struct target target_s390x; extern const struct target target_sh;