Source: gromacs
Severity: normal
X-Debbugs-Cc: wuruil...@loongson.cn
Dear Maintainer,
The attached patch fixes the compilation error problem in the loong64
architecture, and the local compilation passes.
wuruilong
-- System Information:
Debian Release: trixie/sid
APT prefers unreleased
APT policy: (500, 'unreleased'), (500, 'unstable')
Architecture: loong64 (loongarch64)
Kernel: Linux 5.10.0-60.96.0.126.oe2203.loongarch64 (SMP w/32 CPU threads)
Locale: LANG=C, LC_CTYPE=C.UTF-8 (charmap=UTF-8), LANGUAGE not set
Shell: /bin/sh linked to /usr/bin/dash
Init: unable to detect
Description: <short summary of the patch>
TODO: Put a short summary on the line above and replace this paragraph
with a longer explanation of this change. Complete the meta-information
with other relevant fields (see below for details). To make it easier, the
information below has been extracted from the changelog. Adjust it or drop
it.
.
gromacs (2023.3-1) unstable; urgency=medium
.
* New upstream release.
- Remove erfinv-portability.patch, included in this release.
Author: Nicholas Breen <nbr...@debian.org>
---
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Origin: (upstream|backport|vendor|other), (<patch-url>|commit:<commit-id>)
Bug: <upstream-bugtracker-url>
Bug-Debian: https://bugs.debian.org/<bugnumber>
Bug-Ubuntu: https://launchpad.net/bugs/<bugnumber>
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Last-Update: 2024-01-29
--- gromacs-2023.3.orig/src/gromacs/hardware/architecture.h
+++ gromacs-2023.3/src/gromacs/hardware/architecture.h
@@ -46,12 +46,13 @@ namespace gmx
//! Enum for GROMACS CPU hardware detection support
enum class Architecture
{
- Unknown, //!< Not one of the cases below
- X86, //!< X86
- Arm, //!< ARM
- PowerPC, //!< IBM PowerPC
- RiscV32, //!< 32-bit RISC-V
- RiscV64 //!< 64-bit RISC-V
+ Unknown, //!< Not one of the cases below
+ X86, //!< X86
+ Arm, //!< ARM
+ PowerPC, //!< IBM PowerPC
+ RiscV32, //!< 32-bit RISC-V
+ RiscV64, //!< 64-bit RISC-V
+ Loongarch64 //!< 64-bit Loongarch
};
//! Whether the compilation is targeting 32-bit x86.
@@ -81,6 +82,8 @@ static constexpr Architecture c_architec
Architecture::RiscV32;
#elif defined __riscv && defined __riscv_xlen && (__riscv_xlen == 64)
Architecture::RiscV64;
+#elif defined __loongarch__ && defined __loongarch64
+ Architecture::Loongarch64;
#else
Architecture::Unknown;
#endif
--- gromacs-2023.3.orig/src/gromacs/hardware/cpuinfo.cpp
+++ gromacs-2023.3/src/gromacs/hardware/cpuinfo.cpp
@@ -785,6 +785,9 @@ CpuInfo::Vendor detectProcCpuInfoVendor(
{ "riscv64", CpuInfo::Vendor::RiscV64 },
{ "riscv32", CpuInfo::Vendor::RiscV32 },
{ "riscv", CpuInfo::Vendor::RiscV32 }, // Must come after riscv64 to
avoid misidentification
+ { "Loongson", CpuInfo::Vendor::Loongson },
+ { "loongarch64", CpuInfo::Vendor::Loongson },
+ { "loong64", CpuInfo::Vendor::Loongson },
};
// For each label in /proc/cpuinfo, compare the value to the name in the
@@ -1038,6 +1041,10 @@ CpuInfo CpuInfo::detect()
{
result.vendor_ = CpuInfo::Vendor::RiscV64;
}
+ else if (c_architecture == Architecture::Loongarch64)
+ {
+ result.vendor_ = CpuInfo::Vendor::Loongson;
+ }
#if defined __aarch64__ || (defined _M_ARM && _M_ARM >= 8)
result.features_.insert(Feature::Arm_Neon); // ARMv8 always has
Neon
@@ -1100,6 +1107,7 @@ const std::string& CpuInfo::vendorString
{ Vendor::Hygon, "Hygon" },
{ Vendor::RiscV32, "RISC-V 32" },
{ Vendor::RiscV64, "RISC-V 64" },
+ { Vendor::Loongson, "Loongarch" },
};
return vendorStrings.at(vendor_);
--- gromacs-2023.3.orig/src/gromacs/hardware/cpuinfo.h
+++ gromacs-2023.3/src/gromacs/hardware/cpuinfo.h
@@ -88,6 +88,7 @@ public:
Hygon, //!< HygonGenuine
RiscV32, //!< RISC-V 32 bit
RiscV64, //!< RISC-V 64 bit
+ Loongson,//!< Loongson
};
/*! \brief List of CPU features
--- gromacs-2023.3.orig/src/gromacs/timing/include/gromacs/timing/cyclecounter.h
+++ gromacs-2023.3/src/gromacs/timing/include/gromacs/timing/cyclecounter.h
@@ -138,6 +138,9 @@ typedef unsigned long long gmx_cycle
typedef unsigned long gmx_cycles_t;
+#elif defined(__loongarch__) && defined(__GNUC__)
+typedef unsigned long long gmx_cycles_t;
+
#else
/*! \brief Integer-like datatype for cycle counter values
*
@@ -394,6 +397,13 @@ static __inline gmx_cycles_t gmx_cycles_
return ret;
}
+#elif defined __loongarch__ && __loongarch64
+static __inline gmx_cycles_t gmx_cycles_read(void)
+{
+ gmx_cycles_t ret;
+ asm volatile("rdtime.d %0, $r0" : "=r"(ret));
+ return ret;
+}
#else
@@ -565,6 +575,14 @@ static __inline__ bool gmx_cycles_have_c
/* 64-bit RISC-V */
return true;
}
+
+#elif defined __loongarch__ && __loongarch64
+
+static __inline__ bool gmx_cycles_have_counter(void)
+{
+ return true;
+}
+
#else
static bool gmx_cycles_have_counter(void)
{
