Control: tags -1 + patch

I've tested the attached patch and uploaded it to Ubuntu.
Mricron now builds successfully there.
Description: Offset of vstr/vld is limited to +/- 1020
 take care of this during spilling
Origin: upstream, http://svn.freepascal.org/cgi-bin/viewvc.cgi?view=revision&revision=35396
Bug: http://bugs.freepascal.org/view.php?id=31287
Bug-Debian: https://bugs.debian.org/852798
Author: Florian Klämpfl <flor...@freepascal.org>
Last-Update: 2017-02-04
--- a/fpcsrc/compiler/arm/rgcpu.pas
+++ b/fpcsrc/compiler/arm/rgcpu.pas
@@ -189,7 +189,7 @@
 
       { Lets remove the bits we can fold in later and check if the result can be easily with an add or sub }
       a:=abs(spilltemp.offset);
-      if GenerateThumbCode then
+      if GenerateThumbCode or (getregtype(tempreg)=R_MMREGISTER) then
         begin
           {$ifdef DEBUG_SPILLING}
           helplist.concat(tai_comment.create(strpnew('Spilling: Use a_load_const_reg to fix spill offset')));
@@ -243,9 +243,10 @@
     end;
 
 
-   function fix_spilling_offset(offset : ASizeInt) : boolean;
+   function fix_spilling_offset(regtype : TRegisterType;offset : ASizeInt) : boolean;
      begin
        result:=(abs(offset)>4095) or
+         ((regtype=R_MMREGISTER) and (abs(offset)>1020)) or
           ((GenerateThumbCode) and ((offset<0) or (offset>1020)));
      end;
 
@@ -255,7 +256,7 @@
         { don't load spilled register between
           mov lr,pc
           mov pc,r4
-          but befure the mov lr,pc
+          but before the mov lr,pc
         }
         if assigned(pos.previous) and
           (pos.typ=ait_instruction) and
@@ -266,7 +267,7 @@
           (taicpu(pos).oper[1]^.reg=NR_PC) then
           pos:=tai(pos.previous);
 
-        if fix_spilling_offset(spilltemp.offset) then
+        if fix_spilling_offset(getregtype(tempreg),spilltemp.offset) then
           spilling_create_load_store(list, pos, spilltemp, tempreg, false)
         else
           inherited do_spill_read(list,pos,spilltemp,tempreg);
@@ -275,7 +276,7 @@
 
     procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
       begin
-        if fix_spilling_offset(spilltemp.offset) then
+        if fix_spilling_offset(getregtype(tempreg),spilltemp.offset) then
           spilling_create_load_store(list, pos, spilltemp, tempreg, true)
         else
           inherited do_spill_written(list,pos,spilltemp,tempreg);

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