Hello,
package capstone FTBFS again on mips/mipsel.
It seams that adding -Umpis as CFLAGS in Makefile
does not fully solve the issue.
If we add this flag directory in rules for mips,
package builds successfully.
Patch that contains needed changes is attached.
fix-capstone-rules.patch
But, in my opinion, the better (long term) solution would be
to use a different name for union member,
instead of "mips".
Patch that changes name of the union member is attached.
capstone-mips.patch
For both patches,
mips_macro_conflict.patch
could be removed.
Both patches are tested on mips and mipsel.
Best Regards,
Dejan
--- capstone-2.1.2.orig/debian/rules 2014-05-06 19:06:52.000000000 +0000
+++ capstone-2.1.2/debian/rules 2014-07-24 18:16:22.000000000 +0000
@@ -4,6 +4,14 @@
# Uncomment this to turn on verbose mode.
#export DH_VERBOSE=1
+DEB_BUILD_ARCH ?= $(shell dpkg-architecture -qDEB_BUILD_ARCH)
+
+ifneq (,$(filter $(DEB_BUILD_ARCH),mips mipsel))
+CFLAGS = $(shell dpkg-buildflags --get CFLAGS) -Umips
+export CFLAGS
+endif
+
+
%:
dh $@ --with python2
diff -uNr capstone-2.1.2.orig/MCInst.h capstone-2.1.2/MCInst.h
--- capstone-2.1.2.orig/MCInst.h 2014-04-01 02:22:54.000000000 +0000
+++ capstone-2.1.2/MCInst.h 2014-07-24 17:03:22.000000000 +0000
@@ -126,7 +126,7 @@
cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
cs_arm64 arm64; // ARM64 architecture (aka AArch64)
cs_arm arm; // ARM architecture (including Thumb/Thumb2)
- cs_mips mips; // MIPS architecture
+ cs_mips mips_arch; // MIPS architecture
cs_ppc ppc; // PowerPC architecture
};
} cs_insn_flat;
diff -uNr capstone-2.1.2.orig/arch/Mips/MipsInstPrinter.c capstone-2.1.2/arch/Mips/MipsInstPrinter.c
--- capstone-2.1.2.orig/arch/Mips/MipsInstPrinter.c 2014-04-01 02:22:54.000000000 +0000
+++ capstone-2.1.2/arch/Mips/MipsInstPrinter.c 2014-07-24 17:09:33.000000000 +0000
@@ -91,12 +91,12 @@
return;
if (status) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_MEM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = MIPS_REG_INVALID;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = 0;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].type = MIPS_OP_MEM;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].mem.base = MIPS_REG_INVALID;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn.mips_arch.op_count++;
}
}
@@ -228,11 +228,11 @@
reg = Mips_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = reg;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].mem.base = reg;
} else {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_REG;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].reg = reg;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].type = MIPS_OP_REG;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].reg = reg;
+ MI->flat_insn.mips_arch.op_count++;
}
}
}
@@ -254,7 +254,7 @@
}
}
if (MI->csh->detail)
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = imm;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].mem.disp = imm;
} else {
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
@@ -269,9 +269,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].imm = imm;
+ MI->flat_insn.mips_arch.op_count++;
}
}
}
@@ -294,9 +294,9 @@
SStream_concat(O, "-%u", (short int)-imm);
}
if (MI->csh->detail) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = (unsigned short int)imm;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].imm = (unsigned short int)imm;
+ MI->flat_insn.mips_arch.op_count++;
}
} else
printOperand(MI, opNum, O);
@@ -312,9 +312,9 @@
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn.mips_arch.operands[MI->flat_insn.mips_arch.op_count].imm = imm;
+ MI->flat_insn.mips_arch.op_count++;
}
} else
printOperand(MI, opNum, O);
diff -uNr capstone-2.1.2.orig/cs.c capstone-2.1.2/cs.c
--- capstone-2.1.2.orig/cs.c 2014-04-01 02:22:54.000000000 +0000
+++ capstone-2.1.2/cs.c 2014-07-24 17:04:26.000000000 +0000
@@ -567,8 +567,8 @@
count++;
break;
case CS_ARCH_MIPS:
- for (i = 0; i < insn->detail->mips.op_count; i++)
- if (insn->detail->mips.operands[i].type == (mips_op_type)op_type)
+ for (i = 0; i < insn->detail->mips_arch.op_count; i++)
+ if (insn->detail->mips_arch.operands[i].type == (mips_op_type)op_type)
count++;
break;
case CS_ARCH_PPC:
@@ -626,8 +626,8 @@
}
break;
case CS_ARCH_MIPS:
- for (i = 0; i < insn->detail->mips.op_count; i++) {
- if (insn->detail->mips.operands[i].type == (mips_op_type)op_type)
+ for (i = 0; i < insn->detail->mips_arch.op_count; i++) {
+ if (insn->detail->mips_arch.operands[i].type == (mips_op_type)op_type)
count++;
if (count == post)
return i;
diff -uNr capstone-2.1.2.orig/include/capstone.h capstone-2.1.2/include/capstone.h
--- capstone-2.1.2.orig/include/capstone.h 2014-04-01 02:22:54.000000000 +0000
+++ capstone-2.1.2/include/capstone.h 2014-07-24 17:02:55.000000000 +0000
@@ -115,7 +115,7 @@
cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
cs_arm64 arm64; // ARM64 architecture (aka AArch64)
cs_arm arm; // ARM architecture (including Thumb/Thumb2)
- cs_mips mips; // MIPS architecture
+ cs_mips mips_arch; // MIPS architecture
cs_ppc ppc; // PowerPC architecture
};
} cs_detail;
diff -uNr capstone-2.1.2.orig/tests/test_mips.c capstone-2.1.2/tests/test_mips.c
--- capstone-2.1.2.orig/tests/test_mips.c 2014-04-01 02:22:54.000000000 +0000
+++ capstone-2.1.2/tests/test_mips.c 2014-07-24 17:24:29.000000000 +0000
@@ -31,14 +31,14 @@
static void print_insn_detail(cs_insn *ins)
{
- cs_mips *mips = &(ins->detail->mips);
+ cs_mips *mips_arch = &(ins->detail->mips_arch);
- if (mips->op_count)
- printf("\top_count: %u\n", mips->op_count);
+ if (mips_arch->op_count)
+ printf("\top_count: %u\n", mips_arch->op_count);
int i;
- for (i = 0; i < mips->op_count; i++) {
- cs_mips_op *op = &(mips->operands[i]);
+ for (i = 0; i < mips_arch->op_count; i++) {
+ cs_mips_op *op = &(mips_arch->operands[i]);
switch((int)op->type) {
default:
break;
