Hi Keith On Sun, Mar 1, 2020 at 9:44 PM Keith Hui <[email protected]> wrote: > > Hi coreboot folks, > > > I was unable to get any serial output, even with early serial configured. > > > > Z77 power on defaults will see port 80 decoded by LPC according to > > their datasheet, and I found Asus actually included with some boards a > > POST card that plugs into the TPM header, so I'm on the right track. > > Now to see if I can implement the LPC protocol correctly on an Arduino > > Due, chosen for its 84MHz clock and 3.3v operation. > > > > I looked at the source and only see the CONFIG_POST_DEVICE_* options > > used by sb/amd/*/hudson, not by any Intel platform code. > > > > I then looked at the datasheet and the lspci dump with OEM BIOS. I > > would need to do something to device 0x1e.0 (disabled!) and 0x1c.6 > > (PCIe root port 6) and I would need new code that connects to > > CONFIG_POST_DEVICE_*. > > > > I couldn't get LPC bus right on the Due, but I did get serial going. > Initially I didn't get anything past the bootblock signon banner, but > curiously after inserting a stub bootblock_mainboard_init(), I was > able to get serial going and got some logs.
That is good to hear. > My .config is attached, and the boot log follows. TL;DR: Memory init failed. That is not so good to hear. > The RAM are a pair of Samsung 4GB PC3-12800S-11-11-F3 SODIMM modules > on adapters. They did work with OEM firmware. And the adapters have > been used elsewhere with no problems. Alright. That is a rather weird configuration, but I guess it should work. > After replacing the RAM with a pair of OCZ 2GBs I was eventually able > to go all the way through SeaBIOS. It probably booted my > SystemRescueCD on a USB3 stick too, but I cannot say for sure, with > only a black screen throughout out of onboard video. > > OCZ boots with both MRC and native RAM init; Samsung SODIMM fails with both. Uh, interesting. I have seen native raminit fail on some cases, but that MRC also fails is weird. > Where should I look next? > > Thanks > Keith > > --- BEGIN SERIAL LOG --- <snip> > SPD probe channel0, slot0 > SPD probe channel0, slot1 > SPD probe channel0, slot0 > Row addr bits : 15 > Column addr bits : 10 > Number of ranks : 2 > DIMM Capacity : 4096 MB > CAS latencies : 5 6 7 8 9 10 11 > tCKmin : 1.250 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 35.000 ns > tRCmin : 48.125 ns > tRFCmin : 160.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns > channel[0] rankmap = 0x3 > SPD probe channel0, slot1 > Row addr bits : 15 > Column addr bits : 10 > Number of ranks : 2 > DIMM Capacity : 4096 MB > CAS latencies : 5 6 7 8 9 10 11 > tCKmin : 1.250 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 35.000 ns > tRCmin : 48.125 ns > tRFCmin : 160.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns > channel[0] rankmap = 0xf > SPD probe channel1, slot0 > SPD probe channel1, slot1 > SPD probe channel1, slot0 > SPD probe channel1, slot1 > Starting Ivybridge RAM training (0). Note that only Channel 0 has DIMMs. Channel 1 is completely empty, so you are not using dual channel. Note that having two DIMMs on a single channel is extremely unusual. This means, it is probably not well-tested. Try to put the failing DIMMs on separate channels, and try the slots that are furthest away from the CPU. > 100MHz reference clock support: yes > Trying CAS 11, tCK 320. > Found compatible clock, CAS pair. <snip> > Done memory map > Done io registers > Done jedec reset > Done MRS commands > edge write discovery failed: 0, 0, 2 > RAM training failed, trying fallback. This means that, for some reason, one of the memory training algorithms failed. Native raminit has some weird bugs, but it's hard to fix them given the publicly available documentation (none). The raminit then proceeds to do "fallback" mode, which disables the failing channel and tries again. > SPD probe channel0, slot0 > SPD probe channel0, slot1 > SPD probe channel0, slot0 > Row addr bits : 15 > Column addr bits : 10 > Number of ranks : 2 > DIMM Capacity : 4096 MB > CAS latencies : 5 6 7 8 9 10 11 > tCKmin : 1.250 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 35.000 ns > tRCmin : 48.125 ns > tRFCmin : 160.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns > channel[0] rankmap = 0x3 > SPD probe channel0, slot1 > Row addr bits : 15 > Column addr bits : 10 > Number of ranks : 2 > DIMM Capacity : 4096 MB > CAS latencies : 5 6 7 8 9 10 11 > tCKmin : 1.250 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 35.000 ns > tRCmin : 48.125 ns > tRFCmin : 160.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns > channel[0] rankmap = 0xf > SPD probe channel1, slot0 > SPD probe channel1, slot1 > SPD probe channel1, slot0 > SPD probe channel1, slot1 > Starting Ivybridge RAM training (0). > No valid DIMMs found Both DIMMs are on the failing channel. This means that there are no DIMMs to initialize on the other channel, so raminit just halts. > --- END NATIVE RAMINIT LOG --- > > --- BEGIN MRC RAMINIT LOG --- <snip> (MRC raminit debug logs are wet noodles, not really useful) > --- END MRC RAMINIT LOG --- > > [1] This is a message I added in the stub. Best regards, Angel Pons _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
