Marc Jones ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/631
-gerrit commit 3a7234421e81fa4a5b86be12de07c220ac0ccf5b Author: Dave Frodin <[email protected]> Date: Wed Feb 1 16:15:08 2012 -0700 Force SB700 bootblock code to use I/O for PCI config cycles. If PCI config cycles use MMIO instead of I/O in the SB700 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is specified by the mainboards Kconfig. Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672 Signed-off-by: Marc Jones <[email protected]> --- src/southbridge/amd/sb700/bootblock.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 377bffc..370cff9 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -41,15 +41,15 @@ static void sb700_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -59,9 +59,9 @@ static void sb700_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
