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The following commit(s) were added to refs/heads/master by this push:
new 10e33551f hw/mcu/pic32mz: Configure interrupt controller in SystemInit
10e33551f is described below
commit 10e33551ffd3f599fa895950b236443f0e32741e
Author: Jerzy Kasenberg <[email protected]>
AuthorDate: Mon Oct 19 23:15:44 2026 +0200
hw/mcu/pic32mz: Configure interrupt controller in SystemInit
Multi-vector mode, vector spacing and shadow register set assignment
were configured in os_arch_os_init(). When OS_SCHEDULING is 0 (e.g.
bootloader) os_init() is not called, so interrupt controller stayed
in single vector mode with all interrupts dispatched to the same
vector and shadow register sets were not used.
Move this configuration to SystemInit() which is called from startup
code regardless of OS. This makes interrupts use their own vectors
and shadow register sets also in bootloader code.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Jerzy Kasenberg <[email protected]>
---
hw/mcu/microchip/pic32mz/src/system_pic32.c | 18 ++++++++++++++++++
kernel/os/src/arch/pic32/os_arch_pic32.c | 16 ----------------
2 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/mcu/microchip/pic32mz/src/system_pic32.c
b/hw/mcu/microchip/pic32mz/src/system_pic32.c
index 8bd69c1ce..3f6b9e051 100644
--- a/hw/mcu/microchip/pic32mz/src/system_pic32.c
+++ b/hw/mcu/microchip/pic32mz/src/system_pic32.c
@@ -135,6 +135,24 @@ SystemInit(void)
/* Configure System Clock */
SystemClock_Config();
+ /* Multi vector mode */
+ INTCONSET = _INTCON_MVEC_MASK;
+ /* Vector spacing 0x20 */
+ _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
+
+#if defined(PRISS) && (__PIC32_SRS_SET_COUNT == 8)
+ /*
+ * Assign Shadow Register Sets to interrupts:
+ * Interrupt level 0 - (normal execution) SRS 0
+ * Interrupt level 1 - (SW0 - context switch) also SRS 0
+ * Interrupts level 2-7 - SRS 2-7
+ */
+ PRISS = 0x76543200;
+ /* Assign exceptions to SRS 1 */
+ _CP0_SET_SRSCTL((_CP0_GET_SRSCTL() & ~_CP0_SRSCTL_ESS_MASK) |
+ (1 << _CP0_SRSCTL_ESS_POSITION));
+#endif
+
#if !MYNEWT_VAL(MCU_JTAG_ENABLE)
/*
* Programmer may leave JTAGEN set in DEVCFG0, disable JTAG port
diff --git a/kernel/os/src/arch/pic32/os_arch_pic32.c
b/kernel/os/src/arch/pic32/os_arch_pic32.c
index a43daeeab..d831269bd 100644
--- a/kernel/os/src/arch/pic32/os_arch_pic32.c
+++ b/kernel/os/src/arch/pic32/os_arch_pic32.c
@@ -191,22 +191,6 @@ os_arch_os_init(void)
OS_ENTER_CRITICAL(sr);
_CP0_BIC_STATUS(_CP0_STATUS_IPL_MASK);
- /* multi vector mode */
- INTCONSET = _INTCON_MVEC_MASK;
- /* vector spacing 0x20 */
- _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
-
-#if defined(PRISS) && (__PIC32_SRS_SET_COUNT == 8)
- /*
- * Assign Shadow Register Sets to interrupts:
- * Interrupt level 0 - (normal execution) SRS 0
- * Interrupt level 1 - (SW0 - context switch) also SRS 0
- * Interrupts level 2-7 - SRS 2-7
- */
- PRISS = 0x76543200;
- /* Assign exceptions to SRS 1 */
- _CP0_SET_SRSCTL((_CP0_GET_SRSCTL() & ~_CP0_SRSCTL_ESS_MASK) | (1 <<
_CP0_SRSCTL_ESS_POSITION));
-#endif
/* Stop core timer while debugger stops */
_CP0_BIC_DEBUG(_CP0_DEBUG_COUNTDM_MASK);
