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commit 39e946519ba2391530bc5fa05c414a96b36d2a6a Author: Jerzy Kasenberg <[email protected]> AuthorDate: Thu Oct 15 09:02:02 2026 +0200 tinyusb/synopsys: Make ULPI pins configurable ULPI pins were hard-coded. Some signals can be routed to different pins: DIR to PC2 or PI11, NXT to PC3 or PH4 and D4 to PB11 or PB2 (STM32F446). Boards like STM32F746G-DISCO, STM32F769I-DISCO, STM32H743I-EVAL or STM32H747I-DISCO use PH4 and/or PI11. Add syscfg value for every ULPI signal. Default values are pins used so far. Possible pins listed in descriptions come from STM32CubeMX database for all STM32F2/F4/F7/H7 devices with ULPI; all of them use alternate function 10. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/usb/tinyusb/synopsys/src/synopsys.c | 33 ++++++++++++------- hw/usb/tinyusb/synopsys/syscfg.yml | 60 ++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 12 deletions(-) diff --git a/hw/usb/tinyusb/synopsys/src/synopsys.c b/hw/usb/tinyusb/synopsys/src/synopsys.c index b5de86a90..704077aef 100755 --- a/hw/usb/tinyusb/synopsys/src/synopsys.c +++ b/hw/usb/tinyusb/synopsys/src/synopsys.c @@ -37,6 +37,23 @@ #endif #define GPIO_AF_USB MYNEWT_VAL(USB_AF_USB) +#if MYNEWT_VAL(USB_USE_OTG_HS_ULPI) +static const int ulpi_pins[] = { + MYNEWT_VAL(USB_ULPI_CK_PIN), + MYNEWT_VAL(USB_ULPI_STP_PIN), + MYNEWT_VAL(USB_ULPI_DIR_PIN), + MYNEWT_VAL(USB_ULPI_NXT_PIN), + MYNEWT_VAL(USB_ULPI_D0_PIN), + MYNEWT_VAL(USB_ULPI_D1_PIN), + MYNEWT_VAL(USB_ULPI_D2_PIN), + MYNEWT_VAL(USB_ULPI_D3_PIN), + MYNEWT_VAL(USB_ULPI_D4_PIN), + MYNEWT_VAL(USB_ULPI_D5_PIN), + MYNEWT_VAL(USB_ULPI_D6_PIN), + MYNEWT_VAL(USB_ULPI_D7_PIN), +}; +#endif + void OTG_HS_IRQHandler(void) { @@ -62,18 +79,10 @@ tinyusb_hardware_init(void) #endif USB_OTG_CLK_ENABLE(); #if MYNEWT_VAL(USB_USE_OTG_HS_ULPI) - hal_gpio_init_af(MCU_GPIO_PORTA(3), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTA(5), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(0), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(1), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(5), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(10), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(11), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(12), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTB(13), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTC(0), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTC(2), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); - hal_gpio_init_af(MCU_GPIO_PORTC(3), 10, GPIO_NOPULL, GPIO_MODE_AF_PP); + /* All ULPI signals use AF10 on STM32F2/F4/F7/H7 */ + for (int i = 0; i < ARRAY_SIZE(ulpi_pins); ++i) { + hal_gpio_init_af(ulpi_pins[i], 10, GPIO_NOPULL, GPIO_MODE_AF_PP); + } #ifdef __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE(); diff --git a/hw/usb/tinyusb/synopsys/syscfg.yml b/hw/usb/tinyusb/synopsys/syscfg.yml index e902f610d..ad6869108 100644 --- a/hw/usb/tinyusb/synopsys/syscfg.yml +++ b/hw/usb/tinyusb/synopsys/syscfg.yml @@ -48,3 +48,63 @@ syscfg.defs: description: Use ULPI interface value: 0 + USB_ULPI_CK_PIN: + description: > + Pin used for ULPI CK signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PA5 only. + value: 'MCU_GPIO_PORTA(5)' + USB_ULPI_STP_PIN: + description: > + Pin used for ULPI STP signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PC0 only. + value: 'MCU_GPIO_PORTC(0)' + USB_ULPI_DIR_PIN: + description: > + Pin used for ULPI DIR signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PC2 or PI11. + value: 'MCU_GPIO_PORTC(2)' + USB_ULPI_NXT_PIN: + description: > + Pin used for ULPI NXT signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PC3 or PH4. + value: 'MCU_GPIO_PORTC(3)' + USB_ULPI_D0_PIN: + description: > + Pin used for ULPI D0 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PA3 only. + value: 'MCU_GPIO_PORTA(3)' + USB_ULPI_D1_PIN: + description: > + Pin used for ULPI D1 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB0 only. + value: 'MCU_GPIO_PORTB(0)' + USB_ULPI_D2_PIN: + description: > + Pin used for ULPI D2 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB1 only. + value: 'MCU_GPIO_PORTB(1)' + USB_ULPI_D3_PIN: + description: > + Pin used for ULPI D3 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB10 only. + value: 'MCU_GPIO_PORTB(10)' + USB_ULPI_D4_PIN: + description: > + Pin used for ULPI D4 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB11, or PB2 on STM32F446. + value: 'MCU_GPIO_PORTB(11)' + USB_ULPI_D5_PIN: + description: > + Pin used for ULPI D5 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB12 only. + value: 'MCU_GPIO_PORTB(12)' + USB_ULPI_D6_PIN: + description: > + Pin used for ULPI D6 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB13 only. + value: 'MCU_GPIO_PORTB(13)' + USB_ULPI_D7_PIN: + description: > + Pin used for ULPI D7 signal (AF10). Possible pins on + STM32F2/F4/F7/H7: PB5 only. + value: 'MCU_GPIO_PORTB(5)'
