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The following commit(s) were added to refs/heads/master by this push:
new aeafebad6 mcu/stm32h7: Disable caches not enabled by configuration
aeafebad6 is described below
commit aeafebad6b13e2d51e8ca98d5a5e3e0c694b1ced
Author: Jerzy Kasenberg <[email protected]>
AuthorDate: Wed Oct 14 13:29:04 2026 +0200
mcu/stm32h7: Disable caches not enabled by configuration
hal_system_init() only enabled instruction and data cache when
STM32_ENABLE_ICACHE or STM32_ENABLE_DCACHE was set. Boot loader built
with caches enabled leaves them on when it starts application, so
application configured with caches disabled still ran with them
enabled. This breaks code that relies on caches being off, e.g.
stm32_eth driver that does no cache maintenance for DMA descriptors
and buffers placed in cacheable RAM.
Disable cache that is not requested by configuration if it is
enabled at this point.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Jerzy Kasenberg <[email protected]>
---
hw/mcu/stm/stm32h7xx/src/hal_system_init.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/mcu/stm/stm32h7xx/src/hal_system_init.c
b/hw/mcu/stm/stm32h7xx/src/hal_system_init.c
index bec62d8c2..a0309c99a 100644
--- a/hw/mcu/stm/stm32h7xx/src/hal_system_init.c
+++ b/hw/mcu/stm/stm32h7xx/src/hal_system_init.c
@@ -33,14 +33,27 @@ hal_system_init(void)
/* Update SystemCoreClock global variable */
SystemCoreClockUpdate();
+ /*
+ * Boot loader can leave caches enabled, so cache that is not
+ * requested by configuration is disabled here.
+ */
+
/* Enable the instruction cache */
#if MYNEWT_VAL(STM32_ENABLE_ICACHE)
SCB_EnableICache();
+#else
+ if (SCB->CCR & SCB_CCR_IC_Msk) {
+ SCB_DisableICache();
+ }
#endif
/* Enable the data cache */
#if MYNEWT_VAL(STM32_ENABLE_DCACHE)
SCB_EnableDCache();
+#else
+ if (SCB->CCR & SCB_CCR_DC_Msk) {
+ SCB_DisableDCache();
+ }
#endif
/* Relocate the vector table */
